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| MVTX2601 Unmanaged 24-Port 10/100 Mbps Ethernet Switch Data Sheet February 2004 Features * * ntegrated Single-Chip 10/100 Mbps Ethernet Switch 24 10/100 Mbps Autosensing, Fast Ethernet Ports with RMII or Serial Interface (7WS). Each port can independently use one of the two interfaces Serial interface Supports one Frame Buffer Memory domain with SRAM at 100 MHz Supports SRAM domain memory size 1 MB or 2 MB Applies centralized shared memory architecture Up to 64 K MAC addresses Maximum throughput is 2.4 Gbps non-blocking High performance packet forwarding (7.143 M packets per second) at full wire speed Full Duplex Ethernet IEEE 802.3x Flow Control Backpressure flow control for Half Duplex ports Supports Ethernet multicasting and broadcasting and flooding control Supports per-system option to enable flow control for best effort frames even on QoSenabled ports Load sharing among trunked ports can be based on source MAC and/or destination MAC VLAN 1 MCT Ordering Information MVTX2601AG 553 Pin HSBGA -40C to 85C * * * * * Port Mirroring to a dedicated mirroring port or port 23 in unmanaged mode Full set of LED signals provided by a serial interface 2 port trunking groups with up to 4 10/100 ports per group Built-In Self Test for internal and external SRAM Traffic Classification * 4 transmission priorities for Fast Ethernet ports with 2 dropping levels * Classification based on: * * * * * * * * * * * -Port based priority -VLAN Priority field in VLAN tagged frame - DS/TOS field in IP packet - UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range * The precedence of the above classifications is programmable * Frame Data Buffer A SRAM (1 M / 2 M) FDB Interface LED FCB Frame Engine Search Engine MCT Link 24 x 10 / 100 RMII Ports 0 - 23 Management Module Parallel / Serial Figure 1 - MVTX260 1 System Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. MVTX2601 * * Data Sheet QoS Support Supports IEEE 802.1p/Q Quality of Service with 4 transmission priority queues with delay bounded, strict priority, and WFQ service disciplines * * * * Provides 2 levels of dropping precedence with WRED mechanism User controls the WRED thresholds Buffer management: per class and per port buffer reservations Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID * * * Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports Built-in reset logic triggered by system malfunction I2C EEPROM for configuration Description The MVTX2601 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 24 ports at 10/100 Mbps, and a CPU interface for managed and unmanaged switch applications. The chip supports up to 64 K MAC addresses. The centralized shared memory architecture permits a very high performance packet forwarding rate at up to 3.57 1 M packets per second at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching. The Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate bandwidth of 6.4 Gbps to support full wire speed on all ports simultaneously. With delay bounded, strict priority, and/or WFQ transmission scheduling, and WRED dropping schemes, the MVTX2601 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 4 transmission priorities and two levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The MVTX2601 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). The MVTX2601 supports two groups of port trunking/load sharing. Each 10/100 group can contain up to 4 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode, all ports support backpressure flow control to minimize the risk of losing data during long activity bursts. In full-duplex mode IEEE 802.3x flow control is provided. The MVTX2601 also supports a persystem option to enable flow control for best effort frames, even on QoS-enabled ports. The MVTX2601 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are capable of directly interfacing to LVTTL levels. The MVTX2601 is packaged in a 553-pin Ball Grid Array package. 2 Zarlink Semiconductor Inc. MVTX2601 Table of Contents Data Sheet 1.0 Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Frame Data Buffer (FDB) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 10/100 MAC Module (RMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 Configuration Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6 LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.7 Internal Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.2 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 MVTX2601 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.0 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Detailed Memory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Search, Learning and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.1 MAC Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 Priority Classification Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 Port Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 Frame Engine Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.1 FCB Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.2 Rx Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.3 RxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.4 TxQ Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 TxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.0 Quality of Service and Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2 Four QoS Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 Delay Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 Zarlink Semiconductor Inc. MVTX2601 Table of Contents Data Sheet 7.4 Strict Priority and Best Effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5 Weighted Fair Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.6 WRED Drop Threshold Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.7 Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.7.1 Dropping When Buffers Are Scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 MVTX2601 Flow Control Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8.1 Unicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.8.2 Multicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.9 Mapping to IETF Diffserv Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 Features and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.2 Unicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.4 Trunking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.0 Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1 Port Mirroring Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2 Setting Registers for Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.0 GPSI (7WS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.1 GPSI connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.2 SCAN LINK and SCAN COL interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.0 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.1 LED Interface Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.2 Port Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.3 LED Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.1 MVTX2601 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.2 Group 0 Address MAC Ports Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.2.1 ECR1Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.2.2 ECR2Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12.3 Group 1 Address VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.3.1 AVTCL - VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.3.2 AVTCH - VLAN Type Code Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.3.3 PVMAP00_0 - Port 00 Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.3.4 PVMAP00_1 - Port 00 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.3.5 PVMAP00_2 - Port 00 Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.3.6 PVMAP00_3 - Port 00 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.4 Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.4.1 PVMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.5 Group 2 Address Port Trunking Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.5.1 TRUNK0_MODE- Trunk group 0 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.5.2 TRUNK1_MODE - Trunk group 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.6 Group 4 Address Search Engine Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.6.1 TX_AGE - Tx Queue Aging timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.6.2 AGETIME_LOW - MAC address aging time Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.6.3 AGETIME_HIGH -MAC address aging time High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.6.4 SE_OPMODE - Search Engine Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.7 Group 5 Address Buffer Control/QOS Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.7.1 FCBAT - FCB Aging Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.7.2 QOSC - QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.7.3 FCR - Flooding Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.7.4 AVPML - VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 Zarlink Semiconductor Inc. MVTX2601 Table of Contents Data Sheet 12.7.5 AVPMM - VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.7.6 AVPMH - VLAN Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.7.7 TOSPML - TOS Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.7.8 TOSPMM - TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.7.9 TOSPMH - TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.7.10 AVDM - VLAN Discard Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.7.11 TOSDML - TOS Discard Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.7.12 BMRC - Broadcast/Multicast Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.7.13 UCC - Unicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.7.14 MCC - Multicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.7.15 PR100 - Port Reservation for 10/100 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.7.16 SFCB - Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.7.17 C2RS - Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.7.18 C3RS - Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.7.19 C4RS - Class 4 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.7.20 C5RS - Class 5 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.7.21 C6RS - Class 6 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.7.22 C7RS - Class 7 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.7.23 Classes Byte Limit Set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.7.24 Classes Byte Limit Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.7.25 Classes Byte Limit Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.7.26 Classes Byte Limit Set 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.7.27 Classes WFQ Credit Set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.7.28 Classes WFQ Credit Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.7.29 Classes WFQ Credit Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.7.30 Classes WFQ Credit Set 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.7.31 RDRC0 - WRED Rate Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.7.32 RDRC1 - WRED Rate Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.7.33 User Defined Logical Ports and Well Known Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.7.33.1 USER_PORT0_(0~7) - User Define Logical Port (0~7). . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.7.33.2 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority . . . . . . . . . . . . . 54 12.7.33.3 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority . . . . . . . . . . . . . 55 12.7.33.4 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority . . . . . . . . . . . . . 55 12.7.33.5 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority . . . . . . . . . . . . . 55 12.7.33.6 USER_PORT_ENABLE [7:0] - User Define Logic 7 to 0 Port Enables . . . . . . . . . . . . . . . 55 12.7.33.7 WELL_KNOWN_PORT [1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority . . . . . . 55 12.7.33.8 WELL_KNOWN_PORT [3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority . . . . . . 56 12.7.33.9 WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority . . . . . . 56 12.7.33.10 WELL_KNOWN_PORT [7:6] PRIORITY- Well Known Logic Port 7 and 6 Priority . . . . . 56 12.7.33.11 WELL KNOWN_PORT_ENABLE [7:0] - Well Known Logic 7 to 0 Port Enables. . . . . . . 56 12.7.33.12 RLOWL - User Define Range Low Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.7.33.13 RLOWH - User Define Range Low Bit 15:8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.7.33.14 RHIGHL - User Define Range High Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.7.33.15 RHIGHH - User Define Range High Bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.7.33.16 RPRIORITY - User Define Range Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.8 Group 6 Address MISC Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.8.1 MII_OP0 - MII Register Option 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.8.2 MII_OP1 - MII Register Option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.8.3 FEN - Feature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.8.4 MIIC0 - MII Command Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.8.5 MIIC1 - MII Command Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.8.6 MIIC2 - MII Command Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5 Zarlink Semiconductor Inc. MVTX2601 Table of Contents Data Sheet 12.8.7 MIIC3 - MII Command Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.8.8 MIID0 - MII Data Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.8.9 MIID1 - MII Data Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.8.10 LED Mode - LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.8.11 CHECKSUM - EEPROM Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.9 Group 7 Address Port Mirroring Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.9.1 MIRROR1_SRC - Port Mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.9.2 MIRROR1_DEST - Port Mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.9.3 MIRROR2_SRC - Port Mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.9.4 MIRROR2_DEST - Port Mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.10 Group F Address CPU Access Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.10.1 GCR-Global Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.10.2 DCR-Device Status and Signature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.10.3 DCR1-Chip status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.10.4 DPST - Device Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.10.5 DTST - Data read back register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.10.6 PLLCR - PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.10.7 LCLK - LA_CLK delay from internal OE_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.10.8 OECLK - Internal OE_CLK delay from SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.10.9 DA - DA Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.1 BGA Views (Top-View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.1.1 Encapsulated View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.2 Ball - Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.2.1 Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.3 Ball - Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 13.4 AC/DC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.4.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.4.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.4.4 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.5 Local Frame Buffer SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.5.1 Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.6 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.6.1 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.6.2 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.6.3 SCANLINK SCANCOL Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.6.4 MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.6.5 I2C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.6.6 Serial Interface Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6 Zarlink Semiconductor Inc. MVTX2601 List of Figures Data Sheet Figure 1 - MVTX260 1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Data Transfer Format for I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3 - MVTX2601 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only) . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5 - Priority Classification Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6 - Memory Configuration for 1 Bank, 1 Layer, 1 MB Total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7 - Memory Configuration for 1 Bank, 2 Layers, 2 MB Total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8 - Memory Configuration for 1 Bank, 1 Layer, 2 MB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9 - Buffer Partition Scheme Used to Implement MVTX2601 Buffer Management . . . . . . . . . . . . . . . . . . . 26 Figure 10 - GPSI (7WS) Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 11 - SCAN LINK and SCAN COLLISON Status Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 12 - Timing Diagram of LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 13 - Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 14 - Local Memory Interface - Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 15 - Local Memory Interface - Output Valid Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 16 - AC Characteristics - Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 17 - AC Characteristics - Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 18 - AC Characteristics - LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 19 - SCANLINK SCANCOL Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 20 - SCANLINK, SCANCOL Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 21 - MDIO Input Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 22 - MDIO Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 23 - I2C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 24 - I2C Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 25 - Serial Interface Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 26 - Serial Interface Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7 Zarlink Semiconductor Inc. MVTX2601 List of Tables Data Sheet Table 1 - Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2 - PVMAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3 - Supported Memory Configurations (SBRAM Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4 - Options for Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5 - Two Dimensional World Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6 - Four QoS Configurations for a 10/100Mbps Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7 - WRED Drop Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8 - Mapping between MVTX2601 and IETF Diffserv Classes for 10/100 Ports . . . . . . . . . . . . . . . . . . . . . . 27 Table 9 - MVTX2601 Features Enabling IETF Diffserv Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10 - Reset & Bootstrap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 11 - AC Characteristics - Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 12 - AC Characteristics - LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 13 - SCANLINK, SCANCOL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 14 - MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 15 - I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 16 - Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8 Zarlink Semiconductor Inc. MVTX2601 1.0 1.1 Data Sheet Block Functionality Frame Data Buffer (FDB) Interfaces The FDB interface supports pipelined synchronous burst SRAM (SBRAM) memory at 100 MHz. To ensure a nonblocking switch, one memory domain with a 64 bit wide memory bus is required. At 100 MHz, the aggregate memory bandwidth is 6.4 Gbps, which is enough to support 24 10/100 Mbps. The Switching Database is also located in the external SBRAM; it is used for storing MAC addresses and their physical port number. 1.2 10/100 MAC Module (RMAC) The 10/100 Media Access Control module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The MVTX2601 has two interfaces, RMII or Serial (only for 10 M). The 10/100 MAC of the MVTX2601 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for up to 16 total transmissions. The PHY addresses for 24 10/100 MAC are from 08h to 1Fh. 1.3 Configuration Interface Module The MVTX2601 supports a serial and an I2C interface, which provides an easy way to configure the system. Once configured, the resulting configuration can be stored in an I2C EEPROM. 1.4 Frame Engine The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, sent to the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame's priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent. 1.5 Search Engine The Search Engine resolves the frame's destination port or ports according to the destination MAC address (L2). It also performs MAC learning, priority assignment and trunking functions. 1.6 LED Interface The LED interface provides a serial interface for carrying 24 port status signals. 1.7 Internal Memory Several internal tables are required and are described as follows: * * Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame stored in the FDB, e.g., frame size, read/write pointer, transmission priority, etc. MCT Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the external MAC Table. The external MAC table is located in the FDB Memory. Note: the external MAC table is located in the external SBRAM Memory. 9 Zarlink Semiconductor Inc. MVTX2601 2.0 2.1 Data Sheet System Configuration Configuration Mode The MVTX2601 can be configured by EEPROM (24C02 or compatible) via an I2C interface at boot time or via a synchronous serial interface during operation. 2.2 I2C Interface The I2C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request / acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure 2 depicts the data transfer format. START SLAVE ADDRESS R/W ACK DATA 1 (8 bits) ACK DATA 2 ACK DATA M ACK STOP Figure 2 - Data Transfer Format for I 2C Interface 2.2.1 Start Condition Generated by the master (in our case, the MVTX2601). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I2C bus is free, both lines are High. 2.2.2 Address The first byte after the Start condition determines which slave the master will select. The slave in our case is the EEPROM. The first seven bits of the first data byte make up the slave address. 2.2.3 Data Direction The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master transmitter sets this bit to W; a master receiver sets this bit to R. 2.2.4 Acknowledgment Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An acknowledgment pulse follows every byte transfer. If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the transfer. If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let the master generate the Stop condition. 2.2.5 Data After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an acknowledge bit. Data is transferred MSB first. 10 Zarlink Semiconductor Inc. MVTX2601 2.2.6 Stop Condition Data Sheet Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line. The I2C interface serves the function of configuring the MVTX2601 at boot time. The master is the MVTX2601 and the slave is the EEPROM memory. 2.3 Synchronous Serial Interface The synchronous serial interface serves the function of configuring the MVTX2601 not at boot time but via a PC. The PC serves as master and the MVTX2601 serves as slave. The protocol for the synchronous serial interface is nearly identical to the I2C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. The unmanaged MVTX2601 uses a synchronous serial interface to program the internal registers. To reduce the number of signals required, the register address, command and data are shifted in serially through the D0 pin. STROBE- pin is used as the shift clock. AUTOFD- pin is used as data return path. Each command consists of four parts. START pulse Register Address Read or Write command Data to be written or read back Any command can be aborted in the middle by sending a ABORT pulse to the MVTX2601. A START command is detected when D0 is sampled high when STROBE- rise and D0 is sampled low when STROBE- fall. An ABORT command is detected when D0 is sampled low when STROBE- rise and D0 is sampled high when STROBE- fall. 2.3.1 Write Command STROBE2 extra clock cycles after last transfer D0 A0 START A1 A2 ... A9 A10 A11 W D0 D1 D2 D3 D4 D5 DATA D6 D7 ADDRESS COMMAND 11 Zarlink Semiconductor Inc. MVTX2601 2.3.2 Read Command Data Sheet STROBE- D0 A0 A1 A2 A2 A0 A1 A2 START A9 A10 A11 ... A9 A10 A11 R DATA ADDRESS COMMAND AUTOFD- D0 D1 D2 D3 D4 D5 D6 D7 D7 D0 D1 D2 D3 D4 All registers in MVTX2601 can be modified through this synchronous serial interface. 3.0 3.1 MVTX2601 Data Forwarding Protocol Unicast Data Frame Forwarding When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An FCB handle will always be available because of advance buffer reservations. The memory (SRAM) interface consists of a 64-bit bus connected to SRAM bank. The Receive DMA (RxDMA) is responsible for multiplexing the data and the address. On a port's "turn," the RxDMA will move 8 bytes (or up to the end-of-frame) from the port's associated RxFIFO into memory (Frame Data Buffer, or FDB). Once an entire frame has been moved to the FDB and a good end-of-frame (EOF) has been received, the Rx interface makes a switch request. The RxDMA arbitrates among multiple switch requests. The switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination MAC addresses of the frame. The search engine places a switch response in the switch response queue of the frame engine when done. Among other information, the search engine will have resolved the destination port of the frame and will have determined that the frame is unicast. After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has to decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy at the destination. If the frame is not dropped, then the TxQ manager links the frame's FCB to the correct per-portper-class TxQ. Unicast TxQ's are linked lists of transmission jobs, represented by their associated frames' FCB's. There is one linked list for each transmission class for each port. There are 4 transmission classes for each of the 24 10/ 100 ports The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling algorithm. The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port's turn, the TxDMA will move 8 bytes (or up to the EOF) from memory into the port's associated TxFIFO. After reading the EOF, the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release requests. The frame is transmitted from the TxFIFO to the line. 12 Zarlink Semiconductor Inc. MVTX2601 3.2 Multicast Data Frame Forwarding Data Sheet After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the multicast packet's destinations. If so, then the frame is dropped at some destinations but not others and the FCB is not released. If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames). There are 2 multicast queues for each of the 24 10/100 ports. The queue with higher priority has room for 32 entries and the queue with lower priority has room for 64 entries. There is one multicast queue for every two priority classes. For the 10/100 ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one logical queue. The older head of line of the two queues is forwarded first. The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to which the frame is destined. 4.0 4.1 Memory Interface Overview The MVTX2601 provides a 64-bit wide SRAM bank. Each DMA can read and write from the SRAM bank. The following figure provides an overview of the MVTX2601 SRAM bank. SRAM TX DMA 0-7 TX DMA 8-15 TX DMA 16-23 RX DMA 0-7 RX DMA 8-15 RX DMA 16-23 Figure 3 - MVTX2601 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only) 4.2 Detailed Memory Information Because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from memory. 4.3 Memory Requirements To support 64 K MAC address, 2 MB memory is required. When VLAN support is enabled, 512 entries of the MAC address table are used for storing the VLAN ID at VLAN Index Mapping Table. 13 Zarlink Semiconductor Inc. MVTX2601 Data Sheet Up to 1 K Ethernet frame buffers are supported and they will use 1.5 MB of memory. Each frame uses 1536 bytes. The maximum system memory requirement is 2 MB. If less memory is desired, the configuration can scale down. Memory Bank 1M 2M Frame Buffer 1K 2K Table 1 - Memory Configuration Max MAC Address 32 K 64 K 1 M Bank 0.75 M 2 M Bank 1.5 M 0.25 M 0.5 M Frame Data Buffer (FDR) Area MAC Address Control Table (MCT) Area Figure 4 - Memory Map 5.0 5.1 Search Engine Search Engine Overview The MVTX2601 search engine is optimized for high throughput searching, with enhanced features to support: * * * * * * Up to 64 K MAC addresses 2 groups of port trunking Traffic classification into 4 transmission priorities, and 2 drop precedence levels Flooding, Broadcast, Multicast Storm Control MAC address learning and aging Port based VLAN 5.2 Basic Flow Shortly after a frame enters the MVTX2601 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue and the frame engine uses the information provided in that queue for scheduling and forwarding. In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. Among the information extracted are the source and destination MAC addresses, the transmission and discard priorities, whether the frame is unicast or multicast. Requests are sent to the external SRAM to locate the associated entries in the external hash table. 14 Zarlink Semiconductor Inc. MVTX2601 Data Sheet When all the information has been collected from external SRAM, the search engine has to compare the MAC address on the current entry with the MAC address for which it is searching. If it is not a match, the process is repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal to the chip. If the desired MAC address is still not found, then the result is either learning (source MAC address unknown) or flooding (destination MAC address unknown). In addition, port based VLAN information is used to select the correct set of destination ports for the frame (for multicast) or to verify that the frame's destination port is associated with the VLAN (for unicast). If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port number. But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the source and destination MAC addresses. As stated earlier, when all the information is compiled the switch response is generated. The search engine also interacts with the CPU with regard to learning and aging. 5.3 5.3.1 Search, Learning and Aging MAC Search The search block performs source MAC address and destination MAC address searching. As we indicated earlier, if a match is not found, then the next entry in the linked list must be examined and so on until a match is found or the end of the list is reached. The port based VLAN bitmap is used to determine whether the frame should be forwarded to the outgoing port. When the egress port is not included in the ingress port VLAN bitmap, the packet is discarded. The MAC search block is also responsible for updating the source MAC address timestamp and the VLAN port association timestamp, used for aging. 5.3.2 Learning The learning module learns new MAC addresses and performs port change operations on the MCT database. The goal of learning is to update this database as the networking environment changes over time. Learning and port change will be performed based on memory slot availability only. 5.3.3 Aging Aging time is controlled by register 400h and 401h. The aging module scans and ages MCT entries based on a programmable "age out" time interval. As we indicated earlier, the search module updates the source MAC address timestamps for each frame it processes. When an entry is ready to be aged, the entry is removed from the table. 5.4 Quality of Service Quality of Service (QoS) refers to the ability of a network to provide better service to selected network traffic over various technologies. Primary goals of QoS include dedicated bandwidth, controlled jitter and latency (required by some real-time and interactive traffic) and improved loss characteristics. Traditional Ethernet networks have had no prioritization of traffic. Without a protocol to prioritize or differentiate traffic, a service level known as "best effort" attempts to get all the packets to their intended destinations with minimum delay; however, there are no guarantees. In a congested network or when a low-performance switch/router is overloaded, "best effort" becomes unsuitable for delay-sensitive traffic and mission-critical data transmission. 15 Zarlink Semiconductor Inc. MVTX2601 Data Sheet The advent of QoS for packet-based systems accommodates the integration of delay-sensitive video and multimedia traffic onto any existing Ethernet network. It also alleviates the congestion issues that have previously plagued such "best effort" networking systems. QoS provides Ethernet networks with the breakthrough technology to prioritize traffic and ensure that a certain transmission will have a guaranteed minimum amount of bandwidth. Extensive core QoS mechanisms are built into the MVTX2601 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue (WFQ) scheduling at the egress port. In the MVTX2601, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class. Frame and packet scheduling and discarding policies are determined by the class to which the frames and packets belong. For example, the overall service given to frames and packets in the premium class will be better than that given to the standard class; the premium class is expected to experience lower loss rate or delay. The MVTX2601 supports the following QoS techniques: * * * In a port-based setup, any station connected to the same physical port of the switch will have the same transmit priority In a tag-based setup, a 3-bit field in the VLAN tag provides the priority of the packet. This priority can be mapped to different queues in the switch to provide QoS. In a TOS/DS-based set up, TOS stands for "Type of Service" that may include "minimize delay," "maximize throughput" or "maximize reliability." Network nodes may select routing paths or forwarding behaviours that are suitably engineered to satisfy the service request. In a logical port-based set up, a logical port provides the application information of the packet. Certain applications are more sensitive to delays than others; using logical ports to classify packets can help speed up delay sensitive applications such as VoIP. * 5.5 Priority Classification Rule Figure 5 shows the MVTX2601 priority classification rule. Yes Fix Port Priority ? No Use Default Port Settings No IP Yes No TOS Precedence over LAN? (FCR Regiser, Bit 7) No VLAN Tag ? No IP Frame ? Yes Use Default Port Settings Yes Yes No Use TOS Yes Use VLAN Priority Use Logical Port Figure 5 - Priority Classification Rule 16 Zarlink Semiconductor Inc. MVTX2601 5.6 Port Based VLAN Data Sheet An administrator can use the PVMAP Registers to configure the MVTX2601 for port-based VLAN. For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The MVTX2601 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the MVTX2601 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. Destination Port Numbers Bit Map Port Registers Register for Port #0 PVMAP00_0[7:0] to PVMAP00_2[7:0] Register for Port #1 PVMAP01_0[7:0] to PVMAP01_2[7:0] Register for Port #2 PVMAP02_0[7:0] to PVMAP02_2[7:0] ... Register for Port #23 PVMAP23_0[7:0] to PVMAP23_2[7:0] 0 0 0 0 23 0 0 0 ... 2 1 1 0 1 1 0 0 0 0 1 0 Table 2 - PVMAP Register For example, in the above table, a "1" denotes that an outgoing port is eligible to receive a packet from an incoming port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port. In this example: * * * Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2 Data packets received at port #1 are eligible to be sent to outgoing ports 0, and 2 Data packets received at port #2 are not eligible to be sent to ports 0 and 1 5.7 Memory Configurations The MVTX2601 supports the following memory configurations. It supports 1 M and 2 M configurations. 1M (Bootstrap pin TSTOUT7 = open) Two 128 K x 32 SRAM/bank or One 128 K x 64 SRAM/bank Configuration Single Layer (Bootstrap pin TSTOUT13 = open) Double Layer (Bootstrap pin TSTOUT13 = pull down) 2M (Bootstrap pin TSTOUT7 = pull down) Two 256 K x 32 SRAM/bank Connections Connect 0E# and WE# NA Four 128 K x 32 SRAM/bank or Two 128 K x 64 SRAM/bank Connect 0E0# and WE0# Connect 0E1# and WE1# Table 3 - Supported Memory Configurations (SBRAM Mode) 17 Zarlink Semiconductor Inc. MVTX2601 Frame data Buffer Only Bank A 1M (SRAM) MVTX2601 MVTX2602 MVTX2603 MVTX2603 (Gigabit ports in 2 giga mode) MVTX2604 MVTX2604 (Gigabit ports in 2 giga mode) Table 4 - Options for Memory Configuration X X X (125 Mhz) X X 2M (SRAM) X X X X X (125 Mhz) Bank A and Bank B 1 M/bank (SRAM) 2 M/bank (SRAM) Data Sheet Bank A and Bank B 1 M/bank (ZBT SRAM) 2 M/bank (ZBT SRAM) X (125 Mhz) X (125 Mhz) Bank A (1 M One Layer) Data LA_D[63:32] Data LA_D[31:0] SRAM Memory 128 K 32 bits Memory 128 K 32 bits Address LA_A[19:3] Bootstraps: TSTOUT7 = Open, TSTOUT13 = Open, TSTOUT4 = Open Figure 6 - Memory Configuration for 1 Bank, 1 Layer, 1 MB Total 18 Zarlink Semiconductor Inc. MVTX2601 Bank A (2 M Two Layers) Data LA_D[63:32] Data Sheet Data LA_D[31:0] SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits Address LA_A[19:3] Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Pull Down, TSTOUT4 = Open Figure 7 - Memory Configuration for 1 Bank, 2 Layers, 2 MB Total 19 Zarlink Semiconductor Inc. MVTX2601 Bank A (2 M One Layer) Data LA_D[63:32] Data Sheet Data LA_D[31:0] SRAM Memory 256 K 32 bits Memory 256 K 32 bits Address LA_A[20:3] Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Open, TSTOUT4 = Open Figure 8 - Memory Configuration for 1 Bank, 1 Layer, 2 MB 6.0 6.1 Frame Engine Data Forwarding Summary When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface. A switch request is sent to the Search Engine. The Search Engine processes the switch request. A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast and its destination port or ports. A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling Queue (TxSch Q) or Queues. There are four TxSch Q for each 10/100, one for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast or adding an entry to a physical queue if multicast. When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service). The unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The older HOL between the two queues goes first. For 10/100 ports multicast queue 0 is associated with unicast queue 0 and multicast queue 1 is associated with unicast queue 2. The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. 20 Zarlink Semiconductor Inc. MVTX2601 6.2 Frame Engine Details Data Sheet This section briefly describes the functions of each of the modules of the MVTX2601 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames and releases FCB handles upon frame departure. The FCB manager is also responsible for enforcing buffer reservations and limits. The default values can be determined by referring to Chapter 8. In addition, the FCB manager is responsible for buffer aging and for linking unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the bootstrap pin and the aging time is defined in register FCBAT. 6.2.2 Rx Interface The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch request. 6.2.3 RxDMA The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. 6.2.4 TxQ Manager First, the TxQ manager checks the per-class queue status and global reserved resource situation and using this information, makes the frame dropping decision after receiving a switch response. If the decision is not to drop, the TxQ manager requests that the FCB manager link the unicast frame's FCB to the correct per-port-per-class TxQ. If multicast, the TxQ manager writes to the multicast queue for that port and class. The TxQ manager can also trigger source port flow control for the incoming frame's source if that port is flow control enabled. Second, the TxQ manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to the correct port control module. 6.3 Port Control The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control module requests that the buffer be released. 6.4 TxDMA The TxDMA multiplexes data and address from port control and arbitrates among buffer release requests from the port control modules. 7.0 7.1 Quality of Service and Flow Control Model Quality of service is an all-encompassing term for which different people have different interpretations. In general, the approach to quality of service described here assumes that we do not know the offered traffic pattern. We also assume that the incoming traffic is not policed or shaped. Furthermore, we assume that the network manager knows his applications, such as voice, file transfer or web browsing and their relative importance. The manager can then subdivide the applications into classes and set up a service contract with each. The contract may consist of 21 Zarlink Semiconductor Inc. MVTX2601 Data Sheet bandwidth or latency assurances per class. Sometimes it may even reflect an estimate of the traffic mix offered to the switch. As an added bonus, although we do not assume anything about the arrival pattern, if the incoming traffic is policed or shaped, we may be able to provide additional assurances about our switch's performance. Table 5 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form a fourth class with no bandwidth or latency assurances. Total Goals Highest transmission priority, P3 Assured Bandwidth (user defined) Low Drop Probability (low-drop) Apps: phone calls, circuit emulation. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed. Apps: interactive apps, Web business. Latency: < 4-5 ms. Drop: No drop if P2 not oversubscribed. Apps: emails, file backups. Latency: < 16 ms desired, but not critical. Drop: No drop if P1 not oversubscribed. High Drop Probability (high-drop) Apps: training video. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed; first P3 to drop otherwise. Apps: non-critical interactive apps. Latency: < 4-5 ms. Drop: No drop if P2 not oversubscribed; firstP2 to drop otherwise. Apps: casual web browsing. Latency: < 16 ms desired, but not critical. Drop: No drop if P1 not oversubscribed; first to drop otherwise. 50 Mbps Middle transmission priority, P2 37.5 Mbps Low transmission priority, P1 12.5 Mbps Total 100 Mbps Table 5 - Two Dimensional World Traffic A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved class offers traffic at a rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the agreedupon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. However, such leniency must not degrade the quality of service (QoS) received by well-behaved classes. As Table 6 illustrates, the six traffic types may each have their own distinct properties and applications. As shown, classes may receive bandwidth assurances or latency bounds. In the table, P3, the highest transmission class, requires that all frames be transmitted within 1 ms, and receives 50% of the 100 Mbps of bandwidth at that port. Best-effort (P0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any traffic to offer. It is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. In the MVTX2601, each 10/100 Mbps port will support four total classes, and each 1000 Mbps port will support eight classes. We will discuss the various modes of scheduling these classes in the next section. In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should rarely lose packets. But poorly behaved users - users who send frames at too high a rate - will encounter frame loss and the first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped and then all frames in the worst case. 22 Zarlink Semiconductor Inc. MVTX2601 Data Sheet Table 6 shows that different types of applications may be placed in different boxes in the traffic table. For example, casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into the category of low-loss, low-latency traffic. 7.2 Four QoS Configurations There are four basic pieces to QoS scheduling in the MVTX2601: strict priority (SP), delay bound, weighted fair queuing (WFQ), and best effort (BE). Using these four pieces, there are four different modes of operation, as shown in Tables 4 and 5. For 10/100 Mbps ports, these modes are selected by the following registers: QOSC24 [7:6] QOSC28 [7:6] QOSC32 [7:6] QOSC36 [7:6] CREDIT_C00 CREDIT_C10 CREDIT_C20 CREDIT_C30 P3 Op1 (default) Op2 Op3 Op4 WFQ Delay Bound SP SP P2 P1 P0 BE Delay Bound WFQ BE Table 6 - Four QoS Configurations for a 10/100Mbps Port The default configuration for a 10/100 Mbps port is three delay-bounded queues and one best-effort queue. The delay bounds per class are 0.8 ms for P3, 2 ms for P2, and 12.8 ms for P1. Best effort traffic is only served when there is no delay-bounded traffic to be served. We have a second configuration for a 10/100 Mbps port in which there is one strict priority queue, two delay bounded queues and one best effort queue. The delay bounds per class are 3.2 ms for P2 and 12.8 ms for P1. If the user is to choose this configuration, it is important that P3 (SP) traffic be either policed or implicitly bounded (e.g., if the incoming P3 traffic is very light and predictably patterned). Strict priority traffic, if not admissioncontrolled at a prior stage to the MVTX2601 can have an adverse effect on all other classes' performance. The third configuration for a 10/100 Mbps port contains one strict priority queue and three queues receiving a bandwidth partition via WFQ. As in the second configuration, strict priority traffic needs to be carefully controlled. In the fourth configuration, all queues are served using a WFQ service discipline. 7.3 Delay Bound In the absence of a sophisticated QoS server and signaling protocol, the MVTX2601 may not know the mix of incoming traffic ahead of time. To cope with this uncertainty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (HOL) frames. As a result, we assure latency bounds for all admitted frames with high confidence, even in the presence of system-wide congestion. Our algorithm identifies misbehaving classes and intelligently discards frames at no detriment to well-behaved classes. Our algorithm also differentiates between high-drop and low-drop traffic with a weighted random early drop (WRED) approach. Random early dropping prevents congestion by randomly dropping a percentage of high-drop frames even before the chip's buffers are completely full, while still largely sparing lowdrop frames. This allows high-drop frames to be discarded early, as a sacrifice for future low-drop frames. Finally, the delay bound algorithm also achieves bandwidth partitioning among classes. 23 Zarlink Semiconductor Inc. MVTX2601 7.4 Strict Priority and Best Effort Data Sheet When strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. Two of our four QoS configurations include strict priority queues. The goal is for strict priority classes to be used for IETF expedited forwarding (EF), where performance guarantees are required. As we have indicated, it is important that strict priority traffic be either policed or implicitly bounded, so as to keep from harming other traffic classes. When best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other classes have any traffic to offer. Two of our four QoS configurations include best effort queues. The goal is for best effort classes to be used for non-essential traffic, because we provide no assurances about best effort performance. However, in a typical network setting, much best effort traffic will indeed be transmitted and with an adequate degree of expediency. Because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best effort traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before entering the MVTX2601, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To summarize, dropping to enforce bandwidth or delay does not apply to strict priority or best effort queues. We only drop frames from best effort and strict priority queues when global buffer resources become scarce. 7.5 Weighted Fair Queuing In some environments - for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essential, WFQ may be preferable to a delay-bounded scheduling discipline. The MVTX2601 provides the user with a WFQ option with the understanding that delay assurances can not be provided if the incoming traffic pattern is uncontrolled. The user sets four WFQ "weights" such that all weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning with error within 2%. In WFQ mode, though we do not assure frame latency, the MVTX2601 still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. As before, when strict priority is combined with WFQ, we do not have special dropping rules for the strict priority queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. However, we do indeed drop frames from SP queues for global buffer management purposes. In addition, queue P0 for a 10/100 port are treated as best effort from a dropping perspective, though they still are assured a percentage of bandwidth from a WFQ scheduling perspective. What this means is that these particular queues are only affected by dropping when the global buffer count becomes low. 7.6 WRED Drop Threshold Management Support To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified parameters. The following table summarizes the behavior of the WRED logic. In KB (kilobytes) Level 1 N 120 Level 2 N 140 Level 3 N 160 Table 7 - WRED Drop Thresholds Px is the total byte count, in the priority queue x. The WRED logic has three drop levels, depending on the value of N, which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals P3*16+P2*4+P1. If using WFQ scheduling, N equals P3+P2+P1. Each drop level from one to three has defined P3 P2 P1 High Drop X% P3 AKB P2 AKB P1 AKB Y% 100% Low Drop 0% Z% 100% 24 Zarlink Semiconductor Inc. MVTX2601 Data Sheet high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can be discarded. The X, Y Z percent can be programmed by the register RDRC0, RDRC1. In Level 3, all packets are dropped if the bytes in each priority queue exceed the threshold. Parameters A, B, C are the byte count thresholds for each priority queue. They can be programmed by the QOS control register (refer to the register group 5). See Programming Qos Registers Application Note for more information. 7.7 Buffer Management Because the number of FDB slots is a scarce resource and because we want to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept of buffer management into the MVTX2601. Our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool as shown in Figure 9 on page 26. As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first enters the MVTX2601, its destination port and class are as yet unknown and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying. Six reserved sections, one for each of the first six priority classes, ensure a programmable number of FDB slots per class. The lowest two classes do not receive any buffer reservation. Furthermore, even for 10/100 Mbps ports, a frame is stored in the region of the FDB corresponding to its class. As we have indicated, the eight classes use only four transmission scheduling queues for 10/100 Mbps ports, but as far as buffer usage is concerned, there are still eight distinguishable classes. Another segment of the FDB reserves space for each of the 24 ports. One parameter can be set for the source port reservation for 10/100 Mbps. These 24 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. In addition, there is a shared pool which can store any type of frame. The frame engine allocates the frames first in the six priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in the shared poll. Once the shared poll is full the frames are allocated in the section reserved for the source port. The following registers define the size of each section of the frame data buffer: PR100 - Port Reservation for 10/100 Ports SFCB - Share FCB Size C2RS - Class 2 Reserve Size C3RS - Class 3 Reserve Size C4RS - Class 4 Reserve Size C5RS - Class 5 Reserve Size C6RS - Class 6 Reserve Size C7RS- Class 7 Reserve Size 25 Zarlink Semiconductor Inc. MVTX2601 Data Sheet temporary reservation shared pool S per-class reservation per-source reservations (24 10/100 M, CPU) Figure 9 - Buffer Partition Scheme Used to Implement MVTX2601 Buffer Management 7.7.1 Dropping When Buffers Are Scarce Summarizing the two examples of local dropping discussed earlier in this chapter: * * If a queue is a delay-bounded queue, we have a multi level WRED drop scheme, designed to control delay and partition bandwidth in case of congestion If a queue is a WFQ-scheduled queue, we have a multi level WRED drop scheme, designed to prevent congestion In addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. The function of buffer management is to make sure that such dropping causes as little blocking as possible. 7.8 MVTX2601 Flow Control Basics Because frame loss is unacceptable for some applications, the MVTX2601 provides a flow control option. When flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a source port that is sending a packet to this switch to temporarily hold off. While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved or not are halted. A single packet destined for a congested output can block other packets destined for uncongested outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. In the MVTX2601, each source port can independently have flow control enabled or disabled. For flow control enabled ports, by default all frames are treated as lowest priority during transmission scheduling. This is done so that those frames are not exposed to the WRED Dropping scheme. Frames from flow control enabled ports feed to only one queue at the destination, the queue of lowest priority. What this means is that if flow control is enabled for a given source port, then we can guarantee that no packets originating from that port will be lost, but at the possible 26 Zarlink Semiconductor Inc. MVTX2601 Data Sheet expense of minimum bandwidth or maximum delay assurances. In addition, these "downgraded" frames may only use the shared pool or the per-source reserved pool in the FDB; frames from flow control enabled sources may not use reserved FDB slots for the highest six classes (P2-P7). The MVTX2601 does provide a system-wide option of permitting normal QoS scheduling (and buffer use) for frames originating from flow control enabled ports. When this programmable option is active, it is possible that some packets may be dropped even though flow control is on. The reason is that intelligent packet dropping is a major component of the MVTX2601's approach to ensuring bounded delay and minimum bandwidth for high priority flows. 7.8.1 Unicast Flow Control For unicast frames, flow control is triggered by source port resource availability. Recall that the MVTX2601's buffer management scheme allocates a reserved number of FDB slots for each source port. If a programmed number of a source port's reserved FDB slots have been used then flow control Xoff is triggered. Xon is triggered when a port is currently being flow controlled and all of that port's reserved FDB slots have been released. Note that the MVTX2601's per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. 7.8.2 Multicast Flow Control In unmanaged mode, flow control for multicast frames is triggered by a global buffer counter. When the system exceeds a programmable threshold of multicast packets, Xoff is triggered. Xon is triggered when the system returns below this threshold. In addition, each source port has a 23-bit port map recording which port or ports of the multicast frame's fanout were congested at the time Xoff was triggered. All ports are continuously monitored for congestion and a port is identified as uncongested when its queue occupancy falls below a fixed threshold. When all those ports that were originally marked as congested in the port map have become uncongested, then Xon is triggered and the 23-bit vector is reset to zero. 7.9 Mapping to IETF Diffserv Classes For 10/100 Mbps ports, the classes of Table 6 are merged in pairs--one class corresponding to NM+EF, two AF classes and a single BE class. VTX IETF P3 NM+EF P2 AF0 P1 AF1 P0 BE0 Table 8 - Mapping between MVTX2601 and IETF Diffserv Classes for 10/100 Ports 27 Zarlink Semiconductor Inc. MVTX2601 Data Sheet Features of the MVTX2601 that correspond to the requirements of their associated IETF classes are summarized in the table below. Network management (NM) and Expedited forwarding (EF) Assured forwarding (AF) * * * * * * * Best effort (BE) * * * Global buffer reservation for NM and EF Option of strict priority scheduling No dropping if admission controlled Programmable bandwidth partition, with option of WFQ service Option of delay-bounded service keeps delay under fixed levels even if not admission-controlled Random early discard, with programmable levels Global buffer reservation for each AF class Service only when other queues are idle means that QoS not adversely affected Random early discard, with programmable levels Traffic from flow control enabled ports automatically classified as BE Table 9 - MVTX2601 Features Enabling IETF Diffserv Standards 8.0 8.1 Port Trunking Features and Restrictions A port group (i.e., trunk) can include up to 4 physical ports but all of the ports in a group must be in the same MVTX2601. Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address and destination MAC address. Three other options include source MAC address only, destination MAC address only and source port (in bidirectional ring mode only). Load distribution for multicast is performed similarly. The MVTX2601 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking group goes down, the MVTX2601 will automatically redistribute the traffic over to the remaining ports in the trunk. 8.2 Unicast Packet Forwarding The search engine finds the destination MCT entry and if the status field says that the destination port found belongs to a trunk then the group number is retrieved instead of the port number. In addition, if the source address belongs to a trunk then the source port's trunk membership register is checked. A hash key, based on some combination of the source and destination MAC addresses for the current packet, selects the appropriate forwarding port. 8.3 Multicast Packet Forwarding For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the packet based on the VLAN index and hash key. Two functions are required in order to distribute multicast packets to the appropriate destination ports in a port trunking environment. Determining one forwarding port per group. For multicast packets, all but one port per group, the forwarding port, must be excluded. Preventing the multicast packet from looping back to the source trunk. 28 Zarlink Semiconductor Inc. MVTX2601 Data Sheet The search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with the source port. This is because when we select the primary forwarding port for each group, we do not take the source port into account. To prevent this, we simply apply one additional filter, so as to block that forwarding port for this multicast packet. 8.4 Trunking 2 trunk groups are supported. Groups 0 and 1 can trunk up to 4 10/100 ports. The supported combinations are shown in the following table. Group 0 Port 0 Port 1 Port 2 Port 3 Select via trunk0_mode register Group 1 Port 4 Port 5 Port 6 Port 7 Select via trunk1_mode register The trunks are individually enabled/disabled by controlling pin trunk 0,1. 9.0 9.1 Port Mirroring Port Mirroring Features The received or transmitted data of any 10/100 port in the MVTX2601 chip can be "mirrored" to any other port. We support two such mirrored source-destination pairs. A mirror port cannot also serve as a data port. Please refer to the Port Mirroring Application Note for further details. 9.2 * Setting Registers for Port Mirroring MIRROR1_SRC: Sets the source port for the first port mirroring pair. Bits [4:0] select the source port to be mirrored. An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to select between ingress (Rx) or egress (Tx) data. MIRROR1_DEST: Sets the destination port for the first port mirroring pair. Bits [4:0] select the destination port to be mirrored. The default is port 23. MIRROR2_SRC: Sets the source port for the second port mirroring pair. Bits [4:0] select the source port to be mirrored. An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to select between ingress (Rx) or egress (Tx) data. MIRROR2_DEST: Sets the destination port for the second port mirroring pair. Bits [4:0] select the destination port to be mirrored. The default is port 0. * * * 29 Zarlink Semiconductor Inc. MVTX2601 10.0 10.1 Data Sheet GPSI (7WS) Interface GPSI connection The 10/100 RMII ethernet port can function in GPSI (7WS) mode when the corresponding TXEN pin is strapped low with a 1 K pull down resistor. In this mode, the TXD[0], TXD[1], RXD[0] and RXD[1] serve as TX data, TX clock, RX data and RX clock respectively. The link status and collision from the PHY are multiplexed and shifted into the switch device through external glue logic. The duplex of the port can be controlled by programming the ECR register. The GPSI interface can be operated in port based VLAN mode only. CRS_DV RXD[0] RXD[1] TXD[1] TXD[0] TXEN crs rxd rx_clk tx_clk txd txen Port 0 Ethernet PHY link0 col0 link1 260X link2 col1 col2 link23 col23 Port 23 Ethernet PHY SCAN_LINK SCAN_COL SCAN_CLK Link Serializer (CPLD) Collision Serializer (CPLD) Figure 10 - GPSI (7WS) Mode Connection Diagram 30 Zarlink Semiconductor Inc. MVTX2601 10.2 SCAN LINK and SCAN COL interface Data Sheet An external CPLD logic is required to take the link signals and collision signals from the GPSI PHYs and shift them into the switch device. The switch device will drive out a signature to indicate the start of the sequence. After that, the CPLD should shift in the link and collision status of the PHYS as shown in the figure. The extra link status indicates the polarity of the link signal. One indicates the polarity of the link signal is active high. scan_clk scan_link/ scan_col 25 cycles for link / Drived by VTX260x 24 cycles for col Drived by CPLD Total 32 cycles period Figure 11 - SCAN LINK and SCAN COLLISON Status Diagram 11.0 11.1 LED Interface LED Interface Introduction A serial output channel provides port status information from the MVTX2601 chips. It requires three additional pins. * * * LED_CLK at 12.5 MHz LED_SYN a sync pulse that defines the boundary between status frames LED_DATA a continuous serial stream of data for all status LEDs that repeats once every frame time A low cost external device (44 pin PAL) is used to decode the serial data and to drive an LED array for display. This device can be customized for different needs. 11.2 Port Status In the MVTX2601, each port has 8 status indicators, each represented by a single bit. The 8 LED status indicators are: * * * * * * * * Bit 0: Flow control Bit 1:Transmit data Bit 2: Receive data Bit 3: Activity (where activity includes either transmission or reception of data) Bit 4: Link up Bit 5: Speed (1= 100 Mb/s; 0= 10 Mb/s) Bit 6: Full-duplex Bit 7: Collision Eight clocks are required to cycle through the eight status bits for each port. When the LED_SYN pulse is asserted, the LED interface will present 256 LED clock cycles with the clock cycles providing information for the following ports. 31 Zarlink Semiconductor Inc. MVTX2601 Port 0 (10/100): cycles #0 to cycle #7 Port 1 (10/100): cycles#8 to cycle #15 Port 2 (10/100): cycle #16 to cycle #23 ... Port 22 (10/100): cycle #176 to cycle #183 Port 23 (10/100): cycle #184 to cycle #191 Reserved: cycle #192 to cycle #199 Reserved: cycle #200 to cycle #207 Byte 26 (additional status): cycle #208 to cycle #215 Byte 27 (additional status): cycle #216 to cycle #223 Cycles #224 to 256 present data with a value of zero. Byte 26 and byte 27 provides bist status * * * * * * * * * * 26[0]: Reserved 26[1]: Reserved 26[2]: initialization done 26[3]: initialization start 26[4]: checksum ok 26[5]: link_init_complete 26[6]: bist_fail 26[7]: ram_error 27[0]: bist_in_process 27[1]: bist_done Data Sheet 11.3 LED Interface Timing Diagram The signal from the MVTX2601 to the LED decoder is shown in Figure 12. Figure 12 - Timing Diagram of LED Interface 32 Zarlink Semiconductor Inc. MVTX2601 12.0 12.1 Data Sheet Register Definition MVTX2601 Register Description Register Description CPU Addr (Hex) R/W I2C Addr (Hex) Default Notes ETHERNET Port Control Registers Substitute [N] with Port number (0..17h) ECR1P"N" ECR2P"N" Port Control Register 1 for Port N Port Control Register 2 for Port N 000 + 2 x N 001 + 2 x N R/W R/W 000-018 01B-033 020 000 VLAN Control Registers Substitute [N] with Port number (0..17h) AVTCL AVTCH PVMAP"N"_0 PVMAP"N"_1 PVMAP"N"_2 PVMAP"N"_3 PVMODE VLAN Type Code Register Low VLAN Type Code Register High Port "N" Configuration Register 0 Port "N" Configuration Register 1 Port "N" Configuration Register 2 Port "N" Configuration Register 3 VLAN Operating Mode 100 101 102 + 4N 103 + 4N 104 + 4N 105 + 4N 170 R/W R/W R/W R/W R/W R/W R/W 036 037 038-050 053-06B 06E-086 089-0A1 0A4 000 081 0FF 0FF 0FF 007 000 TRUNK Control Registers TRUNK0_MODE TRUNK1_ MODE Trunk Group 0 Mode Trunk Group 1 Mode 203 20B R/W R/W 0A5 0A6 003 003 Search Engine Configurations TX_AGE AGETIME_LOW Transmission Queue Aging Time MAC Address Aging Time Low 325 400 R/W R/W 0A7 0A8 008 2M:05C / 4M:02E 000 000 AGETIME_ HIGH SE_OPMODE MAC Address Aging Time High Search Engine Operating Mode 401 403 R/W R/W 0A9 NA Buffer Control and QOS Control FCBAT QOSC FCR AVPML AVPMM AVPMH TOSPML FCB Aging Timer QOS Control Flooding Control Register VLAN Priority Map Low VLAN Priority Map Middle VLAN Priority Map High TOS Priority Map Low 500 501 502 503 504 505 506 R/W R/W R/W R/W R/W R/W R/W 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0FF 000 008 000 000 000 000 33 Zarlink Semiconductor Inc. MVTX2601 Register TOSPMM TOSPMH AVDM TOSDML BMRC UCC Description TOS Priority Map Middle TOS Priority Map High VLAN Discard Map TOS Discard Map Broadcast/Multicast Rate Control Unicast Congestion Control CPU Addr (Hex) 507 508 509 50A 50B 50C R/W R/W R/W R/W R/W R/W R/W I2C Addr (Hex) 0B1 0B2 0B3 0B4 0B5 0B6 Data Sheet Default 000 000 000 000 000 1M:008 / 2M:010 050 1M:035 / 2M:058 1M:046 / 2M:0E6 000 000 000 000 000 000 000 08F 088 000 000 000 000 000 Notes MCC PR100 Multicast Congestion Control Port Reservation for 10/100 Ports 50D 50E R/W R/W 0B7 0B8 SFCB Share FCB Size 510 R/W 0BA C2RS C3RS C4RS C5RS C6RS C7RS QOSC"N" RDRC0 RDRC1 USER_ PORT"N"_LOW USER_ PORT"N"_HIGH USER_ PORT1:0_ PRIORITY USER_ PORT3:2_ PRIORITY USER_ PORT5:4_ PRIORITY Class 2 Reserve Size Class 3 Reserve Size Class 4 Reserve Size Class 5 Reserve Size Class 6 Reserve Size Class 7 Reserve Size QOS Control (N=0 39) WRED Drop Rate Control 0 WRED Drop Rate Control 1 User Define Logical Port "N" Low (N=0-7) User Define Logical Port "N" High User Define Logic Port 1 and 0 Priority User Define Logic Port 3 and 2 Priority User Define Logic Port 5 and 4 Priority 511 512 513 514 515 516 517-53E 553 554 580 + 2N 581 + 2N 590 591 592 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0BB 0BC 0BD 0BE 0BF 0C0 0C1-0D2 0FB 0FC 0D6-0DD 0DE-0E5 0E6 0E7 0E8 34 Zarlink Semiconductor Inc. MVTX2601 Register USER_ PORT7:6_PRIORIT Y USER_PORT_ ENABLE WLPP10 WLPP32 WLPP54 WLPP76 WLPE RLOWL RLOWH RHIGHL RHIGHH RPRIORITY Description User Define Logic Port 7 and 6 Priority User Define Logic Port Enable Well known Logic Port Priority for 1 and 0 Well known Logic Port Priority for 3 and 2 Well known Logic Port Priority for 5 and 4 Well-known Logic Port Priority for 7&6 Well known Logic Port Enable User Define Range Low Bit7:0 User Define Range Low Bit 15:8 User Define Range High Bit 7:0 User Define Range High Bit 15:8 User Define Range Priority CPU Addr (Hex) 593 R/W R/W I2C Addr (Hex) 0E9 Data Sheet Default 000 Notes 594 595 596 597 598 599 59A 59B 59C 59D 59E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0EA 0EB 0EC 0ED 0EE 0EF 0F4 0F5 0D3 0D4 0D5 000 000 000 000 000 000 000 000 000 000 000 MISC Configuration Registers MII_OP0 MII_OP1 FEN MIIC0 MIIC1 MIIC2 MIIC3 MIID0 MIID1 LED SUM MII Register Option 0 MII Register Option 1 Feature Registers MII Command Register 0 MII Command Register 1 MII Command Register 2 MII Command Register 3 MII Data Register 0 MII Data Register 1 LED Control Register EEPROM Checksum Register 600 601 602 603 604 605 606 607 608 609 60B R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W 0F0 0F1 0F2 N/A N/A N/A N/A N/A N/A 0F3 0FF 000 000 010 000 000 000 000 N/A N/A 000 000 Port Mirroring Controls MIRROR1_SRC Port Mirror 1 Source Port 700 R/W N/A 07F 35 Zarlink Semiconductor Inc. MVTX2601 Register MIRROR1_ DEST MIRROR2_SRC MIRROR2_ DEST Description Port Mirror 1 Destination Port Port Mirror 2 Source Port Port Mirror 2 Destination Port CPU Addr (Hex) 701 702 703 R/W R/W R/W R/W I2C Addr (Hex) N/A N/A N/A Data Sheet Default 017 0FF 000 Notes Device Configuration Register GCR DCR DCR1 DPST DTST DA Global Control Register Device Status and Signature Register Chip status Device Port Status Register Data read back register DA Register F00 F01 F02 F03 F04 FFF R/W RO RO R/W RO RO N/A N/A N/A N/A N/A N/A 000 N/A N/A 000 N/A DA 12.2 12.2.1 * * Group 0 Address MAC Ports Group ECR1Pn: Port N Control Register I2C Address 000-018; CPU Address:0000+2xN (N = port number) Accessed by serial interface and I2C (R/W) 7 6 5 A-FC 1 - Flow Control Off 0 - Flow Control On When Flow Control On: In half duplex mode, the MAC transmitter applies back pressure for flow control In full duplex mode, the MAC transmitter sends Flow Control frames when necessary. The MAC receiver interprets and processes incoming flow control frames. The Flow Control Frame Received counter is incremented whenever a flow control is received. * When Flow Control off: In half duplex mode, the MAC Transmitter does not assert flow control by sending flow control frames or jamming collision. In full duplex mode, the Mac transmitter does not send flow control frames. The MAC receiver does not interpret or process the flow control frames. The Flow Control Frame Received counter is not incremented. Bit [1] 1 - Half Duplex - Only 10/100 mode 0 - Full Duplex * * 4 3 2 1 0 Sp State Bit [0] Port Mode 36 Zarlink Semiconductor Inc. MVTX2601 Bit [2] Bit [4:3] 1 - 10 Mbps 0 - 100 Mbps * * * * Bit [5] * * * * Data Sheet 00 - Automatic Enable Auto Neg. This enables hardware state machine for auto-negotiation. 01 - Limited Disable auto Neg. This disables hardware for speed autonegotiation. Poll MII for link status. 10 - Link Down. Disable auto Neg. state machine and force link down (disable the port) 11 - Link Up. User ERC1 [2:0] for config. Asymmetric Flow Control Enable 0 - Disable asymmetric flow control 1 - Enable asymmetric flow control Asymmetric Flow Control Enable. When this bit is set and flow control is on (bit [0] = 0, don't send out a flow control frame. But MAC receiver interprets and process flow control frames. Default is 0 Bit [7:6] SS - Spanning tree state Default is 11 00 - Blocking: Frame is dropped 01 - Listening: Frame is dropped 10 - Learning: Frame is dropped. Source MAC address is learned. 11 - Forwarding: Frame is forwarded. Source MAC address is learned. 12.2.2 * * ECR2Pn: Port N Control Register I2C Address: 01B-035; CPU Address:0001+2xN Accessed by and serial interface and I2C (R/W) 7 6 5 4 3 Reserve 2 DisL 1 Ftf 0 Futf QoS Sel Bit [0]: * Filter untagged frame (Default 0) * 0: Disable * 1: All untagged frames from this port are discarded Bit [1]: * Filter Tag frame (Default 0) * 0: Disable * 1: All tagged frames from this port are discarded Bit [2]: * Learning Disable (Default 0) * 1 Learning is disabled on this port * 0 Learning is enabled on this port Bit [3]: * Must be set to `1' 37 Zarlink Semiconductor Inc. MVTX2601 Bit [5:4:] * * * Data Sheet * * * * Bit [7:6] QOS mode selection (Default 00) Determines which of the 4 sets of QoS settings is used for 10/100 ports. Note that there are 4 sets of per-queue byte thresholds, and 4 sets of WFQ ratios programmed. These bits select among the 4 choices for each 10/100 port. Refer to QoS Application Note. 00: select class byte limit set 0 and classes WFQ credit set 0 01: select class byte limit set 1 and classes WFQ credit set 1 10: select class byte limit set 2 and classes WFQ credit set 2 11: select class byte limit set 3 and classes WFQ credit set 3 Reserved 12.3 12.3.1 * * Group 1 Address VLAN Group AVTCL - VLAN Type Code Register Low I2C Address 036; CPU Address:h100 Accessed by serial interface and I2C (R/W) Bit [7:0]: * LANType_LOW: Lower 8 bits of the VLAN type code (Default 00) 12.3.2 * * AVTCH - VLAN Type Code Register High I 2C Address 037; CPU Address:h101 Accessed by serial interface and I2C (R/W) Bit [7:0]: * VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 81) 12.3.3 * * PVMAP00_0 - Port 00 Configuration Register 0 I2C Address 038, CPU Address:h102) Accessed by serial interface and I2C (R/W) Bit [7:0]: * VLAN Mask for ports 7 to 0 (Default FF) This register indicates the legal egress ports. A "1" on bit 7 means that the packet can be sent to port 7. A "0" on bit 7 means that any packet destined to port 7 will be discarded. This register works with registers 1 and 2 to form a 24-bit mask to all egress ports. 12.3.4 * * PVMAP00_1 - Port 00 Configuration Register 1 I2C Address h53, CPU Address:h103 Accessed by serial interface and I2C (R/W) Bit [7:0]: * VLAN Mask for ports 15 to 8 (Default is FF) 38 Zarlink Semiconductor Inc. MVTX2601 12.3.5 * * Data Sheet PVMAP00_2 - Port 00 Configuration Register 2 I2C Address h6E, CPU Address:h104 Accessed by serial interface and I2C (R/W) Bit [7:0]: * VLAN Mask for ports 23 to 16 (Default FF) 12.3.6 * * PVMAP00_3 - Port 00 Configuration Register 3 I2C Address h89, CPU Address:h105) Accessed by serial interface and I2C (R/W) 7 FP en Bit [2:0]: Bit [5:3]: 6 Drop 5 3 2 0 Default tx priority Reserved (Default 7) Default Transmit priority. Used when Bit [7] = 1 (Default 0) * 000 Transmit Priority Level 0 (Lowest) * 001 Transmit Priority Level 1 * 010 Transmit Priority Level 2 * 011 Transmit Priority Level 3 * 100 Transmit Priority Level 4 * 101 Transmit Priority Level 5 * 110 Transmit Priority Level 6 * 111 Transmit Priority Level 7 (Highest) Default Discard priority (Default 0) * 0 - Discard Priority Level 0 (Lowest) * 1 - Discard Priority Level 7(Highest) Enable Fix Priority (Default 0) * 0 Disable fix priority. All frames are analyzed. Transmit Priority and Discard Priority are based on VLAN Tag, TOS field or Logical Port. * 1 Transmit Priority and Discard Priority are based on values programmed in bit [6:3] Bit [6]: Bit [7]: 12.4 * * * * * * * * * * * * Port Configuration Register PVMAP01_0,1,2,3 I2C Address h39,54,6F,8A; CPU Address:h106,107,108,109) PVMAP02_0,1,2,3 I2C Address h3A,55,70,8B; CPU Address:h10A, 10B, 10C, 10D) PVMAP03_0,1,2,3 I2C Address h3B,56,71,8C; CPU Address:h10E, 10F, 110, 111) PVMAP04_0,1,2,3 I2C Address h3C,57,72,8D; CPU Address:h112, 113, 114, 115) PVMAP05_0,1,2,3 I2C Address h3D,58,73,8E; CPU Address:h116, 117, 118, 119) PVMAP06_0,1,2,3 I2C Address h3E,59,74,8F; CPU Address:h11A, 11B, 11C, 11D) PVMAP07_0,1,2,3 I2C Address h3F,5A,75,90; CPU Address:h11E, 11F, 120, 121) PVMAP08_0,1,2,3 I2C Address h40,5B,76,91; CPU Address:h122, 123, 124, 125) PVMAP09_0,1,2,3 I2C Address h41,5C,77,92; CPU Address:h126, 127, 128, 129) PVMAP10_0,1,2,3 I2C Address h42,5D,78,93; CPU Address:h12A, 12B, 12C, 12D) PVMAP11_0,1,2,3 I2C Address h43,5E,79,94; CPU Address:h12E, 12F, 130, 131) PVMAP12_0,1,2,3 I2C Address h44,5F,7A,95; CPU Address:h132, 133, 134, 135) 39 Zarlink Semiconductor Inc. MVTX2601 * * * * * * * * * * * PVMAP13_0,1,2,3 PVMAP14_0,1,2,3 PVMAP15_0,1,2,3 PVMAP16_0,1,2,3 PVMAP17_0,1,2,3 PVMAP18_0,1,2,3 PVMAP19_0,1,2,3 PVMAP20_0,1,2,3 PVMAP21_0,1,2,3 PVMAP22_0,1,2,3 PVMAP23_0,1,2,3 I 2C I 2C I 2C I 2C I 2C I 2C I 2C I 2C I 2C I 2C I 2C Address Address Address Address Address Address Address Address Address Address Address h45,60,7B,96; CPU Address:h136, 137, 138, 139) h46,61,7C,97; CPU Address:h13A, h13B, 13C, 13D) h47,62,7D,98; CPU Address:h13E, 13F, 140, 141) h48,63,7E,99; CPU Address:h142, 143, 144, 145) h49,64,7F,9A; CPU Address:h146, 147, 148, 149) h4A,65,80,9B; CPU Address:h14A, 14B, 14C, 14D) h4B,66,81,9C; CPU Address:h14E, 14F, 150, 151) h4C,67,82,9D; CPU Address:h152, 153, 154, 155) h4D,68,83,9E; CPU Address:h156, 157, 158, 159) h4E,69,84,9F; CPU Address:h15A, 15B, 15C, 15D) h4F,6A,85,A0; CPU Address:h15E, 15F, 160, 161) Data Sheet 12.4.1 * * PVMODE I2C Address: h0A4, CPU Address:h170 Accessed by serial interface, and I2C (R/W) 7 5 4 SM0 Bit [0]: Bit [1]: * * * Reserved Must be `0' Slow learning * Same function as SE_OP MODE bit 7. Either bit can enable the function; both need to be turned off to disable the feature. 3 2 DF 1 SL 0 Bit [2]: * Disable dropping of frames with destination MAC addresses 0180C2000001 to 0180C200000F (Default = 0) * 0: Drop all frames in this range * 1: Disable dropping of frames in this range Bit [3]: Bit [4]: * * Reserved Support MAC address 0 * 0: MAC address 0 is not learned. * 1: MAC address 0 is learned. Bit [7:5]: * Reserved 12.5 12.5.1 * * Group 2 Address Port Trunking Group TRUNK0_MODE- Trunk group 0 mode I2C Address h0A5; CPU Address:203 Accessed by serial interface and I2C (R/W) 7 4 3 2 1 0 Hash Select Port Select 40 Zarlink Semiconductor Inc. MVTX2601 Bit [1:0]: * Data Sheet Port selection in unmanaged mode. Input pin TRUNK0 enable/disable trunk group 0. * * * * 00 01 10 11 Reserved Port 0 and 1 are used for trunk0 Port 0,1 and 2 are used for trunk0 Port 0,1,2 and 3 are used for trunk0 Bit [3:2] * Hash Select. The Hash selected is valid for Trunk 0, 1 and 2. (Default 00) * * * * 00 01 10 11 for Use Source and Destination Mac Address for hashing Use Source Mac Address for hashing Use Destination Mac Address for hashing Use source destination MAC address and ingress physical port number hashing 12.5.2 * * TRUNK1_MODE - Trunk group 1 mode I2C Address h0A6; CPU Address:20B Accessed by serial interface and I2C (R/W) 7 2 1 0 Port Select Bit [1:0]: * Port selection in unmanaged mode. Input pin TRUNK1 enable/disable trunk group 1. * * * * 00 01 10 11 Reserved Port 4 and 5 are used for trunk1 Reserved Port 4, 5, 6 and 7 are used for trunk1 12.6 12.6.1 * * Group 4 Address Search Engine Group TX_AGE - Tx Queue Aging timer I2C Address: h07;CPU Address:h325 Accessed by serial interface (RW) 7 6 5 Tx Queue Agent 0 * * * Bit [5:0]: Unit of 100 ms (Default 8) Disable transmission queue aging if value is zero. Aging timer for all ports and queues. For no packet loss flow control, this register must be set to 0 12.6.2 * * * * AGETIME_LOW - MAC address aging time Low I2C Address h0A8; CPU Address:h400 Accessed by serial interface and I2C (R/W) Bit [7:0] Low byte of the MAC address aging timer MAC address aging is enable/disable by boot strap TSTOUT9 41 Zarlink Semiconductor Inc. MVTX2601 12.6.3 * * * * * Data Sheet AGETIME_HIGH -MAC address aging time High I2C Address h0A9; CPU Address h401 Accessed by serial interface and I2C (R/W) Bit [7:0]: High byte of the MAC address aging timer The default setting provide 300 seconds aging time. Aging time is based on the following equation: {AGETIME_TIME,AGETIME_LOW} X (# of MAC address entries in the memory x 100 sec). Number of MAC entries = 32 K when 1 MB is used. Number of MAC entries = 64 K when 2 MB is used. 12.6.4 * * * SE_OPMODE - Search Engine Operation Mode CPU Address:h403 Accessed by serial interface (R/W) {SE_OPMODE} X(# of entries 100 usec) 7 SL Bit [5:0]: Bit [6]: * * 6 DMS Reserved Disable MCT speedup aging * 1 - Disable speedup aging when MCT resource is low * 0 - Enable speedup aging when MCT resource is low 5 0 Bit [7]: * Slow Learning * 1- Enable slow learning. Learning is temporary disabled when search demand is high * 0 - Learning is performed independent of search demand 42 Zarlink Semiconductor Inc. MVTX2601 12.7 12.7.1 * Data Sheet Group 5 Address Buffer Control/QOS Group FCBAT - FCB Aging Timer I2C Address h0AA; CPU Address:h500 7 FCBAT Bit [7:0]: * * FCB Aging time. Unit of 1ms. (Default FF) This function is for buffer aging control. It is used to configure the aging time, and can be enabled/ disabled through bootstrap pin. It is not recommended to use this function for normal operation. 0 12.7.2 * * QOSC - QOS Control IC Address h0AB; CPU Address:h501 Accessed by serial interface and I2C (R/W) 7 Tos-d Bit [0]: Bit [4]: 6 Tos-p * * * * * * * * * * * 5 4 VF1c 3 1 0 L QoS frame lost is OK. Priority will be available for flow control enabled source only when this bit is set (Default 0) Per VLAN Multicast Flow Control (Default 0) 0 - Disable 1 - Enable Reserved Select TOS bits for Priority (Default 0) 0 - Use TOS [4:2] bits to map the transmit priority 1 - Use TOS [7:5] bits to map the transmit priority Select TOS bits for Drop Priority (Default 0) 0 - Use TOS[4:2] bits to map the drop priority 1 - Use TOS[7:5] bits to map the drop priority Bit [5]: Bit [6]: Bit [7]: 12.7.3 * * FCR - Flooding Control Register I2C Address h0AC; CPU Address:h502 Accessed by serial interface and I2C (R/W) 7 Tos 6 TimeBase 4 3 U2MR 0 43 Zarlink Semiconductor Inc. MVTX2601 Bit [3:0]: * Data Sheet U2MR: Unicast to Multicast Rate. Units in terms of time base defined in bits [6:4]. This is used to limit the amount of flooding traffic. The value in U2MR specifies how many packets are allowed to flood within the time specified by bit [6:4]. To disable this function, program U2MR to 0. (Default = 8) TimeBase: Bit [6:4]: * 000 = 100 us 001 = 200 us 010 = 400 us 011 = 800 us 100 = 1.6 ms 101 = 3.2 ms 110 = 6.4 ms 111 = 100 us (same as 000) * Bit [7]: * (Default = 000) Select VLAN tag or TOS (IP packets) to be preferentially picked to map transmit priority and drop priority (Default = 0). * 0 - Select VLAN Tag priority field over TOS * 1 - Select TOS over VLAN tag priority field 12.7.4 * * AVPML - VLAN Priority Map I2C Address h0AD; CPU Address:h503 Accessed by serial interface and I2C (R/W) 7 6 VP2 5 VP1 3 2 VP0 0 Registers AVPML, AVPMM, and AVPMH allow the eight VLAN priorities to map into eight internal level transmit priorities. Under the internal transmit priority, seven is highest priority where as zero is the lowest. This feature allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map VLAN priority 0 into internal transmit priority 7. The new priority is used inside the 2601. When the packet goes out it carries the original priority. Bit [2:0]: Bit [5:3]: Bit [7:6]: * * * Priority when the VLAN tag priority field is 0 (Default 0) Priority when the VLAN tag priority field is 1 (Default 0) Priority when the VLAN tag priority field is 2 (Default 0) 44 Zarlink Semiconductor Inc. MVTX2601 12.7.5 * * Data Sheet AVPMM - VLAN Priority Map I2C Address h0AE, CPU Address:h504 Accessed by serial interface and I2C (R/W) 7 VP5 6 VP4 4 3 VP3 1 0 VP2 Map VLAN priority into eight level transmit priorities: Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: * * * * Priority when the VLAN tag priority field is 2 (Default 0) Priority when the VLAN tag priority field is 3 (Default 0) Priority when the VLAN tag priority field is 4 (Default 0) Priority when the VLAN tag priority field is 5 (Default 0) 12.7.6 * * AVPMH - VLAN Priority Map I2C Address h0AF, CPU Address:h505 Accessed by serial interface and I2C (R/W) 7 VP7 5 4 VP6 2 1 VP5 0 Map VLAN priority into eight level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: * * * Priority when the VLAN tag priority field is 5 (Default 0) Priority when the VLAN tag priority field is 6 (Default 0) Priority when the VLAN tag priority field is 7 (Default 0) 12.7.7 * * TOSPML - TOS Priority Map I2C Address h0B0, CPU Address:h506 Accessed by serial interface and I2C (R/W) 7 TP2 6 5 TP1 3 2 TP0 0 Map TOS field in IP packet into eight level transmit priorities Bit [2:0]: Bit [5:3]: Bit [7:6]: * * * Priority when the TOS field is 0 (Default 0) Priority when the TOS field is 1 (Default 0) Priority when the TOS field is 2 (Default 0) 45 Zarlink Semiconductor Inc. MVTX2601 12.7.8 * * Data Sheet TOSPMM - TOS Priority Map I2C Address h0B1, CPU Address:h507 Accessed by serial interface and I2C (R/W) 7 TP5 6 TP4 4 3 TP3 1 0 TP2 Map TOS field in IP packet into four level transmit priorities Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: * * * * Priority when the TOS field is 2 (Default 0) Priority when the TOS field is 3 (Default 0) Priority when the TOS field is 4 (Default 0) Priority when the TOS field is 5 (Default 0) 12.7.9 * * TOSPMH - TOS Priority Map I2C Address h0B2, CPU Address:h508 Accessed by serial interface and I2C (R/W) 7 TP7 5 4 TP6 2 1 TP5 0 Map TOS field in IP packet into four level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: * * * Priority when the TOS field is 5 (Default 0) Priority when the TOS field is 6 (Default 0) Priority when the TOS field is 7 (Default 0) 12.7.10 * * AVDM - VLAN Discard Map I2C Address h0B3, CPU Address:h509 Accessed by serial interface and I2C (R/W) 7 FDV7 6 FDV6 5 FDV5 4 FDV4 3 FDV3 2 FDV2 1 FDV1 0 FDV0 Map VLAN priority into frame discard when low priority buffer usage is above threshold Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: * * * * * * Frame drop priority when VLAN tag priority field is 0 (Default 0) Frame drop priority when VLAN tag priority field is 1 (Default 0) Frame drop priority when VLAN tag priority field is 2 (Default 0) Frame drop priority when VLAN tag priority field is 3 (Default 0) Frame drop priority when VLAN tag priority field is 4 (Default 0) Frame drop priority when VLAN tag priority field is 5 (Default 0) 46 Zarlink Semiconductor Inc. MVTX2601 Bit [6]: Bit [7]: * * Frame drop priority when VLAN tag priority field is 6 (Default 0) Frame drop priority when VLAN tag priority field is 7 (Default 0) Data Sheet 12.7.11 * * TOSDML - TOS Discard Map I2C Address h0B4, CPU Address:h50A Accessed by serial interface and I2C (R/W) 7 FDT7 6 FDT6 5 FDT5 4 FDT4 3 FDT3 2 FDT2 1 FDT1 0 FDT0 Map TOS into frame discard when low priority buffer usage is above threshold Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: * * * * * * * * Frame drop priority when TOS field is 0 (Default 0) Frame drop priority when TOS field is 1 (Default 0) Frame drop priority when TOS field is 2 (Default 0) Frame drop priority when TOS field is 3 (Default 0) Frame drop priority when TOS field is 4 (Default 0) Frame drop priority when TOS field is 5 (Default 0) Frame drop priority when TOS field is 6 (Default 0) Frame drop priority when TOS field is 7 (Default 0) 12.7.12 * * BMRC - Broadcast/Multicast Rate Control I2C Address h0B5, CPU Address:h50B) Accessed by serial interface and I2C (R/W) 7 Broadcast Rate 4 3 Multicast Rate 0 * This broadcast and multicast rate defines for each port the number of packet allowed to be forwarded within a specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field to 0. Timebase is based on register 502 [6:4]. Bit [3:0] : * Multicast Rate Control Number of multicast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0). Broadcast Rate Control Number of broadcast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0) Bit [7:4] : * 47 Zarlink Semiconductor Inc. MVTX2601 12.7.13 * * Data Sheet UCC - Unicast Congestion Control I2C Address h0B6, CPU Address: 50C Accessed by serial interface and I2C (R/W) 7 Unicast congest threshold Bit [7:0] : * Number of frame count. Used for best effort dropping at B% when destination port's best effort queue reaches UCC threshold and shared pool is all in use. Granularity 1 frame. (Default: h10 for 2 MB or h08 for 1 MB) 0 12.7.14 * * MCC - Multicast Congestion Control I2C Address h0B7, CPU Address: 50D Accessed by serial interface and I2C (R/W) 7 FC reaction prd Bit [4:0]: * 5 4 Multicast congest threshold 0 In multiples of two. Used for triggering MC flow control when destination multicast port's best effort queue reaches MCC threshold. (Default 0x10) Flow control reaction period (Default 2) Granularity 4 uSec. Bit [7:5]: * 12.7.15 * * PR100 - Port Reservation for 10/100 ports I2C Address h0B8, CPU Address 50E Accessed by serial interface and I2C (R/W) 7 Buffer low thd Bit [3:0]: * * 4 3 0 SP Buffer reservation Per port buffer reservation. Define the space in the FDB reserved for each 10/100 port. Expressed in multiples of 4 packets. For each packet 1536 bytes are reserved in the memory. Expressed in multiples of 4 packets. Threshold for dropping all best effort frames when destination port best efforts queues reach UCC threshold and shared pool all used and source port reservation is at or below the PR100[7:4] level. Also the threshold for initiating UC flow control. Default: * h58 for configuration with 2 MB; * h35 for configuration with 1 MB; Bits [7:4]: * * 48 Zarlink Semiconductor Inc. MVTX2601 12.7.16 * * Data Sheet SFCB - Share FCB Size I2C Address h0BA), CPU Address 510 Accessed by serial interface and I2C (R/W) 7 Shared buffer size Bits [7:0]: * * Expressed in multiples of 4 packets. Buffer reservation for shared pool. Default: * hE6 for configuration with memory of 2 MB; * h46 for configuration with memory of 1 MB; 0 12.7.17 * * C2RS - Class 2 Reserve Size I2C Address h0BB, CPU Address 511 Accessed by serial interface and I2C (R/W) 7 Class 2 FCB Reservation 0 * Buffer reservation for class 2 (third lowest priority). Granularity 1. (Default 0) 12.7.18 C3RS - Class 3 Reserve Size I2C Address h0BC, CPU Address 512 Accessed by serial interface and I2C (R/W) 7 Class 3 FCB Reservation * Buffer reservation for class 3. Granularity 1. (Default 0) 0 12.7.19 * * C4RS - Class 4 Reserve Size I2C Address h0BD, CPU Address 513 Accessed by serial interface and I2C (R/W) 7 Class 4 FCB Reservation 0 * Buffer reservation for class 4. Granularity 1. (Default 0) 49 Zarlink Semiconductor Inc. MVTX2601 12.7.20 * * Data Sheet C5RS - Class 5 Reserve Size I2C Address h0BE; CPU Address 514 Accessed by serial interface and I2C (R/W) 7 Class 5 FCB Reservation 0 * Buffer reservation for class 5. Granularity 1. (Default 0) 12.7.21 * * C6RS - Class 6 Reserve Size I2C Address h0BF; CPU Address 515 Accessed by serial interface and I2C (R/W) 7 Class 6 FCB Reservation 0 * Buffer reservation for class 6 (second highest priority). Granularity 1. (Default 0) 12.7.22 * * C7RS - Class 7 Reserve Size I2C Address h0C0; CPU Address 516 Accessed by serial interface and I2C (R/W) 7 Class 7 FCB Reservation 0 * Buffer reservation for class 7 (highest priority). Granularity 1. (Default 0) 12.7.23 * Classes Byte Limit Set 0 Accessed by serial interface and I2C (R/W): C -- QOSC00 - BYTE_C01 (I2C Address h0C1, CPU Address 517) B -- QOSC01 - BYTE_C02 (I2C Address h0C2, CPU Address 518) A -- QOSC02 - BYTE_C03 (I2C Address h0C3, CPU Address 519) QOSC00 through QOSC02 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Drop (WRED) Scheme described in Chapter 7.7. There are four such sets of values A-C specified in Classes Byte Limit Set 0, 1, 2 and 3. Each 10/ 100 port can choose one of the four Byte Limit Sets as specified by the QoS Select field located in bits 5 to 4 of the ECR2n register. The values A-C are per-queue byte thresholds for random early drop. QOSC02 represents A and QOSC00 represents C. Granularity when Delay bound is used: QOSC02: 128 bytes, QOSC01: 256 bytes. QOSC00: 512 bytes. Granularity when WFQ is used: QOSC02: 512 bytes, QOSC01: 512 bytes, QOSC00: 512 bytes. 50 Zarlink Semiconductor Inc. MVTX2601 12.7.24 * Data Sheet Classes Byte Limit Set 1 Accessed by serial interface and I2C (R/W): C - QOSC03 - BYTE_C11 (I2C Address h0C4, CPU Address 51a) B - QOSC04 - BYTE_C12 (I2C Address h0C5, CPU Address 51b) A - QOSC05 - BYTE_C13 (I2C Address h0C6, CPU Address 51c) QOSC03 through QOSC05 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Detect (WRED) Scheme. Granularity when Delay bound is used: QOSC05: 128 bytes, QOSC04: 256 bytes. QOSC03: 512 bytes. Granularity when WFQ is used: QOSC05: 512 bytes, QOSC04: 512 bytes, QOSC03: 512 bytes. 12.7.25 * Classes Byte Limit Set 2 Accessed by serial interface and I2C (R/W): C - QOSC06 - BYTE_C21 (CPU Address 51d) B - QOSC07 - BYTE_C22 (CPU Address 51e) A - QOSC08 - BYTE_C23 (CPU Address 51f) QOSC06 through QOSC08 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Detect (WRED) Scheme. Granularity when Delay bound is used: QOSC08: 128 bytes, QOSC07: 256 bytes. QOSC06: 512 bytes. Granularity when WFQ is used: QOSC08: 512 bytes, QOSC07: 512 bytes, QOSC06: 512 bytes. 12.7.26 * Classes Byte Limit Set 3 Accessed by serial interface and I2C (R/W): C - QOSC09 - BYTE_C31 (CPU Address 520) B - QOSC10 - BYTE_C32 (CPU Address 521) A - QOSC11 - BYTE_C33 (CPU Address 522) QOSC09 through QOSC011 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Detect (WRED) Scheme. Granularity when Delay bound is used: QOSC11: 128 bytes, QOSC10: 256 bytes. QOSC09: 512 bytes. Granularity when WFQ is used: QOSC11: 512 bytes, QOSC10: 512 bytes, QOSC09: 512 bytes. 12.7.27 * Classes WFQ Credit Set 0 Accessed by serial interface (R/W) W0 - QOSC24[5:0] - CREDIT_C00 (CPU Address 52f) W1 - QOSC25[5:0] - CREDIT_C01 (CPU Address 530) W2 - QOSC26[5:0] - CREDIT_C02 (CPU Address 531) W3 - QOSC27[5:0] - CREDIT_C03 (CPU Address 532) QOSC24 through QOSC27 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1 and their sum must be 64. QOSC27 corresponds to W3 and QOSC24 corresponds to W0. QOSC24[7:6]: Priority service type for the ports select this parameter set. Option 1 to 4. 51 Zarlink Semiconductor Inc. MVTX2601 QOSC25[7]: Priority service allow flow control for the ports select this parameter set. QOSC25[6]: Flow control pause best effort traffic only Both flow control allow and flow control best effort only can take effect only the priority type is WFQ. Data Sheet 12.7.28 * Classes WFQ Credit Set 1 Accessed by serial interface (R/W) W0 - QOSC28[5:0] - CREDIT_C10 (CPU Address 533) W1 - QOSC29[5:0] - CREDIT_C11 (CPU Address 534) W2 - QOSC30[5:0] - CREDIT_C12 (CPU Address 535) W3 - QOSC31[5:0] - CREDIT_C13 (CPU Address 536) QOSC28 through QOSC31 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1 and their sum must be 64. QOSC31 corresponds to W3 and QOSC28 corresponds to W0. QOSC28[7:6]: Priority service type for the ports select this parameter set. Option 1 to 4. QOSC29[7]: Priority service allow flow control for the ports select this parameter set. QOSC29[6]: Flow control pause best effort traffic only 12.7.29 * Classes WFQ Credit Set 2 Accessed by serial interface (R/W) W0 - QOSC32[5:0] - CREDIT_C20 (CPU Address 537) W1 - QOSC33[5:0] - CREDIT_C21 (CPU Address 538) W2 - QOSC34[5:0] - CREDIT_C22 (CPU Address 539) W3 - QOSC35[5:0] - CREDIT_C23 (CPU Address 53a) QOSC35 through QOSC32 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1 and their sum must be 64. QOSC35 corresponds to W3 and QOSC32 corresponds to W0. QOSC32[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4. QOSC33[7]: Priority service allow flow control for the ports select this parameter set. QOSC33[6]: Flow Control pause best effort traffic only 12.7.30 * Classes WFQ Credit Set 3 Accessed by serial interface (R/W) W0 - QOSC36[5;0] - CREDIT_C30 (CPU Address 53b) W1 - QOSC37[5:0] - CREDIT_C31 (CPU Address 53c) W2 - QOSC38[5:0] - CREDIT_C32 (CPU Address 53d) W3 - QOSC39[5:0] - CREDIT_C33 (CPU Address 53e) QOSC39 through QOSC36 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1 and their sum must be 64. QOSC39 corresponds to W3 and QOSC36 corresponds to W0. QOSC36[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4. 52 Zarlink Semiconductor Inc. MVTX2601 QOSC37[7]: Priority service allow flow control for the ports select this parameter set. QOSC37[6]: Flow Control pause best effort traffic only Data Sheet 12.7.31 * * RDRC0 - WRED Rate Control 0 I2C Address 0FB, CPU Address 553 Accessed by serial Interface and IcC (R/W) 7 X Rate Bits [7:4]: Bits [3:0]: * * 4 3 Y Rate Corresponds to the frame drop percentage X% for WRED. Granularity 6.25%. Corresponds to the frame drop percentage Y% for WRED. Granularity 6.25%. 0 See Programming QoS Registers application note for more information. 12.7.32 * * RDRC1 - WRED Rate Control 1 I2C Address 0FC, CPU Address 554 Accessed by serial Interface and I2C (R/W) 7 Z Rate Bits [7:4]: Bits [3:0]: * * 4 3 B Rate Corresponds to the frame drop percentage Z% for WRED. Granularity 6.25%. Corresponds to the best effort frame drop percentage B%, when shared pool is all in use and destination port best effort queue reaches UCC. Granularity 6.25%. 0 See Programming QoS Register Application Note for more information. 12.7.33 User Defined Logical Ports and Well Known Ports The MVTX2601 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports and 1 User Defined Range. The 8 Well Known Ports supported are: * * * * * * * * 0:23 1:512 2:6000 3:443 4:111 5:22555 6:22 7:554 53 Zarlink Semiconductor Inc. MVTX2601 Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Enable can individually turn on/off each Well Known Port if desired. Data Sheet Well_Known_Port_ Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7 registers. Two registers are required to be programmed for the logical port number. The respective priority can be programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via User_Port_Enable register. The User Defined Range provides a range of logical port numbers with the same priority level. Programming is similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper limit is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than the upper limit and more than the lower limit will use the priority specified in RPRIORITY. 12.7.33.1 * * * * * * * * * USER_PORT0_(0~7) - User Define Logical Port (0~7) USER_PORT_0 - I2C Address h0D6 + 0DE; CPU Address 580(Low) + 581(High) USER_PORT_1 - I2C Address h0D7 + 0DF; CPU Address 582 + 583 USER_PORT_2 - I2C Address h0D8 + 0E0; CPU Address 584 + 585 USER_PORT_3 - I2C Address h0D9 + 0E1; CPU Address 586 + 587 USER_PORT_4 - I2C Address h0DA + 0E2; CPU Address 588 + 589 USER_PORT_5 - I2C Address h0DB + 0E3; CPU Address 58a + 58b USER_PORT_6 - I2C Address h0DC + 0E4; CPU Address 58c + 58d USER_PORT_7 - I2C Address h0DD + 0E5; CPU Address 58e + 58f Accessed by serial interface and I2C (R/W) 7 TCP/UDP Logic Port Low 0 7 TCP/UDP Logic Port High * 0 (Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the definition of eight separate ports. 12.7.33.2 * * USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority I2C Address h0E6, CPU Address 590 Accessed by serial interface and I2C (R/W) 7 Priority 1 5 4 Drop 3 Priority 0 1 0 Drop * The chip allows the definition of the priority Bits [3:0]: Bits [7:4]: * * Priority setting, transmission + dropping, for logic port 0 Priority setting, transmission + dropping, for logic port 1 (Default 00) 54 Zarlink Semiconductor Inc. MVTX2601 12.7.33.3 * * Data Sheet USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority I2C Address h0E7, CPU Address 591 Accessed by serial interface and I2C (R/W) 7 Priority 3 5 4 Drop 3 Priority 2 1 0 Drop 12.7.33.4 * * USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority I2C Address h0E8, CPU Address 592 Accessed by serial interface and I2C (R/W) 7 Priority 5 5 4 Drop 3 Priority 4 1 0 Drop * (Default 00) 12.7.33.5 * * USER_PORT_[7:6]_PRIORITY - USER DEFINE LOGIC PORT 7 AND 6 PRIORITY I2C Address h0E9, CPU Address 593 Accessed by serial interface and I2C (R/W) 7 Priority 7 5 4 Drop 3 Priority 6 1 0 Drop * (Default 00) 12.7.33.6 * * USER_PORT_ENABLE [7:0] - User Define Logic 7 to 0 Port Enables I2C Address h0EA, CPU Address 594 Accessed by serial interface and I2C (R/W) 7 P7 6 P6 5 P5 4 P4 3 P3 2 P2 1 P1 0 P0 * (Default 00) 12.7.33.7 * * WELL_KNOWN_PORT [1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority I2C Address h0EB, CPU Address 595 Accessed by serial interface and I2C (R/W) 7 Priority 1 5 4 Drop 3 Priority 0 1 0 Drop * * * Priority 0 - Well known port 23 for telnet applications. Priority 1 - Well known port 512 for TCP/UDP (Default 00) 55 Zarlink Semiconductor Inc. MVTX2601 12.7.33.8 * * I2C Address h0EC, CPU Address 596 Accessed by serial interface and I2C (R/W) 7 Priority 3 * * * 5 4 Drop 3 Priority 2 1 0 Drop Data Sheet WELL_KNOWN_PORT [3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority Priority 2 - Well known port 6000 for XWIN. Priority 3 - Well known port 443 for http. sec (Default 00) 12.7.33.9 * * WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority I2C Address h0ED, CPU Address 597 Accessed by serial interface and I2C (R/W) 7 Priority 5 5 4 Drop 3 Priority 4 1 0 Drop * * * Priority 4 - Well known port 111 for sun rpe. Priority 5 - Well known port 22555 for IP Phone call setup. (Default 00) 12.7.33.10 * * WELL_KNOWN_PORT [7:6] PRIORITY- Well Known Logic Port 7 and 6 Priority I2C Address h0EE, CPU Address 598 Accessed by serial interface and I2C (R/W) 7 Priority 7 5 4 Drop 3 Priority 6 1 0 Drop * * * Priority 6 - Well known port 22 for ssh. Priority 7 - Well known port 554 for rtsp. (Default 00) 12.7.33.11 * * WELL KNOWN_PORT_ENABLE [7:0] - Well Known Logic 7 to 0 Port Enables I2C Address h0EF, CPU Address 599 Accessed by serial interface and I2C (R/W) 7 P7 * 1 - Enable * 0 - Disable 6 P6 5 P5 4 P4 3 P3 2 P2 1 P1 0 P0 * Default 00) 56 Zarlink Semiconductor Inc. MVTX2601 12.7.33.12 * * * Data Sheet RLOWL - User Define Range Low Bit 7:0 I2C Address h0F4, CPU Address: 59a Accessed by serial interface and I2C (R/W) (Default 00) 12.7.33.13 * * * RLOWH - User Define Range Low Bit 15:8 I2C Address h0F5, CPU Address: 59b Accessed by serial interface and I2C (R/W) (Default 00) 12.7.33.14 * * * RHIGHL - User Define Range High Bit 7:0 I2C Address h0D3, CPU Address: 59c Accessed by serial interface and I2C (R/W) (Default 00) 12.7.33.15 * * * RHIGHH - User Define Range High Bit 15:8 I2C Address h0D4, CPU Address: 59d Accessed by serial interface and I2C (R/W) (Default 00) 12.7.33.16 * * RPRIORITY - User Define Range Priority I2C Address h0D5, CPU Address: 59e Accessed by serial interface and I2C (R/W) 7 4 3 Range Transmit Priority 0 Drop * RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit [3:1] Bits [0]: * * Transmit Priority Drop Priority 12.8 12.8.1 * * Group 6 Address MISC Group MII_OP0 - MII Register Option 0 I2C Address F0, CPU Address:h600 Accessed by serial interface and I2C (R/W) 7 hfc 6 1prst 5 DisJ 4 Vendor Spc. Reg Addr 0 57 Zarlink Semiconductor Inc. MVTX2601 Bits [7]: * Half duplex flow control feature * 0 = Half duplex flow control always enable * 1 = Half duplex flow control by negotiation Data Sheet Bits [6]: Bits [5]: * * Link partner reset auto-negotiate disable Disable jabber detection. This is for HomePNA application or any serial operation slower than 10 Mbps. * 1 = disable * 0 = enable Bit [4:0]: * Vendor specified link status register address (null value means don't use it) (Default 00); used when the Linkup bit position in the PHY is non-standard. 12.8.2 * * MII_OP1 - MII Register Option 1 I2C Address F1, CPU Address:h601 Accessed by serial interface and I2C (R/W) 7 Speed bit location Bits [3:0]: Bits [7:4]: * * 4 3 Duplex bit location 0 Duplex bit location in vendor specified register Speed bit location in vendor specified register (Default 00) 12.8.3 * * FEN - Feature Register I2C Address F2, CPU Address:h602) Accessed by serial interface and I2C (R/W) 7 DML Bits [1:0]: Bit [2]: 6 MII * * * * * Reserved (Default 0) Support DS EF Code. (Default 0) When 101110 is detected in DS field (TOS [7:2]), the frame priority is set for 110 and drop is set for 0. Reserved (Default 010) Disable MII Management State Machine * 0: Enable MII Management State Machine (Default 0) * 1: Disable MII Management State Machine 5 3 2 DS 1 0 Bit [5:3]: Bit [6]: Bit [7]: * Disable using MCT link list structure * 0: Enable using MCT Link List structure (Default 0) * 1: Disable using MCT Link List structure 58 Zarlink Semiconductor Inc. MVTX2601 12.8.4 * * * Data Sheet MIIC0 - MII Command Register 0 CPU Address:h603 Accessed by serial interface only (R/W) Bit [7:0] MII Data [7:0] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then program MII command. 12.8.5 * * * MIIC1 - MII Command Register 1 CPU Address:h604 Accessed by serial interface only (R/W) Bit [7:0] MII Data [15:8] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. 12.8.6 * * MIIC2 - MII Command Register 2 CPU Address:h605 Accessed by serial interface only (R/W) 7 6 Mii OP Bits [4:0]: Bit [6:5] 5 4 Register address * REG_AD - Register PHY Address * OP - Operation code "10" for read command and "01" for write command 0 Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. Writing to this register will initiate a serial management cycle to the MII management interface. For detail information, please refer to the PHY Control Application Note. 12.8.7 * * MIIC3 - MII Command Register 3 CPU Address:h606 Accessed by serial interface only (R/W) 7 Rdy Bits [4:0]: Bit [6] Bit [7] 6 Valid * * * 5 4 PHY address PHY_AD - 5 Bit PHY Address VALID - Data Valid from PHY (Read Only) RDY - Data is returned from PHY (Ready Only) 0 Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. 59 Zarlink Semiconductor Inc. MVTX2601 12.8.8 * * * Data Sheet MIID0 - MII Data Register 0 CPU Address:h607 Accessed by serial interface only (RO) Bit [7:0] MII Data [7:0] 12.8.9 * * * MIID1 - MII Data Register 1 CPU Address:h608 Accessed by serial interface only (RO) Bit [7:0] MII Data [15:8] 12.8.10 * * LED Mode - LED Control CPU Address:h609 Accessed by serial interface and I2C (R/W) 7 5 4 Clock rate Bit [0] Bit [2:1]: * * Reserved (Default 0) Hold time for LED signal (Default= 00) 00 = 8 msec 01 = 16 msec 10 = 32 msec 11 = 64 msec LED clock frequency (Default 0) For 100 MHz SCLK, 00 = 100 M/8 = 12.5 MHz 01 = 100 M/16 = 6.25 MHz 10 = 100 M/32 = 3.125 MHz 11 = 100 M/64 = 1.5625 MHz For 125 MHz SCLK 00 = 125 M/64 = 1953 KHz 10 = 125 M/512 = 244 KHz Bit [7:6]: * 01 = 125 M/128 = 977 KHz 11 = 125 M/1024 = 122 KHz 3 2 Hold Time 1 0 Bit [4:3]: * Reserved. Must be 0. (Default 0) 12.8.11 * * CHECKSUM - EEPROM Checksum I2C Address FF, CPU Address:h60b Accessed by serial interface and I2C (R/W) Bit [7:0]: * (Default 0) Before requesting that the MVTX2601 updates the EEPROM device, the correct checksum needs to be calculated and written into this checksum register. When the MVTX2601 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the MVTX2601 does not start and pin CHECKSUM_OK is set to zero. The checksum formula is: FF I2C register = 0 I=0 60 Zarlink Semiconductor Inc. MVTX2601 12.9 12.9.1 * * Data Sheet Group 7 Address Port Mirroring Group MIRROR1_SRC - Port Mirror source port CPU Address 700 Accessed by serial interface (R/W) (Default 7F) 7 6 5 I/O Bit [4:0]: Bit [5]: Bit [7]: * * * * 4 Src Port Select 0 Source port to be mirrored. Use illegal port number to disable mirroring. 1 - select ingress data 0 - select egress data Must be `1' 12.9.2 * * MIRROR1_DEST - Port Mirror destination CPU Address 701 Accessed by serial interface (R/W) (Default 17) 7 5 4 Dest Port Select Bit [4:0]: * Port Mirror Destination 0 12.9.3 * * MIRROR2_SRC - Port Mirror source port CPU Address 702 Accessed by serial interface (R/W) (Default FF) 7 6 5 I/O Bit [4:0]: Bit [5]: Bit [7] * * * * 4 Src Port Select 0 Source port to be mirrored. Use illegal port number to disable mirroring. 1 - select ingress data 0 - select egress data Must be 1 61 Zarlink Semiconductor Inc. MVTX2601 12.9.4 * * Data Sheet MIRROR2_DEST - Port Mirror destination CPU Address 703 Accessed by serial interface (R/W) (Default 00) 7 5 4 Dest Port Select Bit [4:0]: * Port Mirror Destination 0 12.10 12.10.1 * * Group F Address CPU Access Group GCR-Global Control Register CPU Address: hF00 Accessed by serial interface. (R/W) 7 4 3 Reset Bit [0]: Bit [1]: Bit [2]: * * * * * * * * * 2 Bist 1 SR 0 SC Store configuration (Default = 0) Write `1' followed by `0' to store configuration into external EEPROM Store configuration and reset (Default = 0) Write `1' to store configuration into external EEPROM and reset chip Start BIST (Default = 0) Write `1' followed by `0' to start the device's built-in self-test. The result is found in the DCR register. Soft Reset (Default = 0) Write `1' to reset chip Reserved Bit [3]: Bit [7:4]: 62 Zarlink Semiconductor Inc. MVTX2601 12.10.2 * * Data Sheet DCR-Device Status and Signature Register CPU Address: hF01 Accessed by serial interface. (RO) 7 6 5 4 3 RE 2 BinP 1 BR 0 BW Revision Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [5:4]: Bit [7:6]: * * * * * * * * * * * * * Signature 1: Busy writing configuration to I2C 0: Not busy writing configuration to I2C 1: Busy reading configuration from I2C 0: Not busy reading configuration from I2C 1: BIST in progress 0: BIST not running 1: RAM Error 0: RAM OK Device Signature 01: MVTX2601 device Revision 00: Initial Silicon 01: XA1 Silicon 12.10.3 * * DCR1-Chip status CPU Address: hF02 Accessed by serial interface (RO) 7 CIC Bit [7] * Chip initialization completed 6 0 63 Zarlink Semiconductor Inc. MVTX2601 12.10.4 * * Data Sheet DPST - Device Port Status Register CPU Address:hF03 Accessed by serial interface (R/W) Bit [4:0]: * Read back index register. This is used for selecting what to read back from DTST. (Default 00) - 5'b00000 - Port 0 Operating mode and Negotiation status - 5'b00001 - Port 1 Operating mode/Neg status - 5'b00010 - Port 2 Operating mode/Neg status - 5'b00011 - Port 3 Operating mode/Neg status - 5'b00100 - Port 4 Operating mode/Neg status - 5'b00101 - Port 5 Operating mode/Neg status - 5'b00110 - Port 6 Operating mode/Neg status - 5'b00111 - Port 7 Operating mode/Neg status - 5'b01000 - Port 8 Operating mode/Neg status - 5'b01001 - Port 9 Operating mode/Neg status - 5'b01010 - Port 10 Operating mode/Neg status - 5'b01011 - Port 11 Operating mode/Neg status - 5'b01100 - Port 12 Operating mode/Neg status - 5'b01101 - Port 13 Operating mode/Neg status - 5'b01110 - Port 14 Operating mode/Neg status - 5'b01111 - Port 15 Operating mode/Neg status - 5'b10000 - Port 16 Operating mode/Neg status - 5'b10001 - Port 17 Operating mode/Neg status - 5'b10010 - Port 18 Operating mode/Neg status - 5'b00011 - Port 19 Operating mode/Neg status - 5'b10100 - Port 20 Operating mode/Neg status - 5'b10101 - Port 21 Operating mode/Neg status - 5'b10110 - Port 22 Operating mode/Neg status - 5'b10111 - Port 23 Operating mode/Neg status 64 Zarlink Semiconductor Inc. MVTX2601 12.10.5 * * * Data Sheet DTST - Data read back register CPU Address: hF04 Accessed by serial interface (RO) This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Control Application Note. 7 4 3 Inkdn 2 FE 1 Fdpx 0 FcEn When bit is 1: * Bit [0] - Flow control enable * Bit [1] - Full duplex port * Bit [2] - Fast Ethernet port * Bit [3] - Link is down * Bit [7:4] - Reserved 12.10.6 * * PLLCR - PLL Control Register CPU Address: hF05 Accessed by serial interface (RW) Bit [3] Bit [7] Must be '1' Selects strap option or LCLK/OECLK registers 0 - Strap option (default) 1 - LCLK/OECLK registers 12.10.7 * * LCLK - LA_CLK delay from internal OE_CLK CPU Address: hF06 Accessed by serial interface (RW) PD[12:10] 000b 001b 010b 011b 100b 101b 110b 111b LCLK 80h 40h 20h 10h 08h 04h 02h 01h Delay 8 Buffers Delay 7 Buffers Delay 6 Buffers Delay 5 Buffers Delay (Recommend) 4 Buffers Delay 3 Buffers Delay 2 Buffers Delay 1 Buffers Delay The LCLK delay from SCLK is the sum of the delay programmed in here and the delay in OECLK register. 65 Zarlink Semiconductor Inc. MVTX2601 12.10.8 * * Data Sheet OECLK - Internal OE_CLK delay from SCLK CPU Address: hF07 Accessed by serial interface (RW) The OE_CLK is used for generating the OE0 and OE1 signals. PD[15:13] 000b 001b 010b 011b 100b 101b 110b 111b OECLK 80h 40h 20h 10h 08h 04h 02h 01h Delay 8 Buffers Delay 7 Buffers Delay (Recommend) 6 Buffers Delay 5 Buffers Delay 4 Buffers Delay 3 Buffers Delay 2 Buffers Delay 1 Buffers Delay 12.10.9 * * * DA - DA Register CPU Address: hFFF Accessed by CPU and serial interface (RO) Always return 8'h DA. Indicate the serial port connection is good. 66 Zarlink Semiconductor Inc. MVTX2601 13.0 13.1 13.1.1 1 A B 2 Data Sheet BGA and Ball Signal Descriptions BGA Views (Top-View) Encapsulated View 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 LA_D LA_D LA_D LA_D LA_D LA_A LA_O LA_A LA_A LA_A LA_A LA_D LA_D LA_D LA_D LA_D OE_C LA_C TRUN MIRR MIRR SCL 4 7 10 13 15 4 E0_ 8 13 16 19 33 36 39 42 45 LK0 LK0 K1 OR4 OR1 TO S D A S T R O T ST 7 BE U D0 TSTO TSTO UT8 UT3 LA_D LA_D LA_D LA_D LA_D LA_D LA_A LA_O LA_A LA_A LA_A LA_A LA_D LA_D LA_D LA_D LA_D OE_C LA_C LA_D MIRR MIRR RESE RESE 1 3 6 9 12 14 DSC_ E1_ 7 12 15 18 32 35 38 41 44 LK1 LK1 62 OR5 OR2 RVED RVED C LA_C LA_D LA_D LA_D LA_D LA_D LA_A LA_O LA_W T_MO LA_A LA_A LA_A LA_A LA_D LA_D LA_D LA_D OE_C LA_C P_D TRUN MIRR MIRR AUTO TSTO TSTO TSTO TSTO LK 0 2 5 8 11 3 E_ E_ DE1 11 14 17 20 34 37 40 43 LK2 LK2 K0 OR3 OR0 FD UT11 UT9 UT4 UT0 D AGN LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_A LA_A LA_W LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_D SCAN SCAN TSTO TSTO TSTO TSTO TSTO TSTO D 17 19 21 23 25 27 29 31 6 10 E0_ 49 51 53 55 57 59 61 63 47 COL CLK UT14 UT13 UT12 UT10 UT5 UT1 AN S C A N T S T O R E S E R E S E S CO D T S T O T S T O LI N K U T15 R VED R VED ME UT6 UT2 RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED VDD VDD VDD VDD RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED VDD VDD VSS VSS VSS VSS VSS VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VCC RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RVE D RESE VCC RVE D RESE VCC RVE D RESE VCC RVE D RESE RVED RESE RVED RESE RVED RESE RVED MDIO RESE RVED MDC M_CL K _ _ _ _ _ _ _ _ A_W _ _ _ _ _ _ _ RES _ E S C L K L A 6 D L A 8 D L A 0 D L A 2 D L A 4 D L A 6 D L A 8 D L A 0 D L A _ A L A _ A LE 1 _ L A 8 D L A 0 D L A 2 D L A 4 D L A 6 D L A 8 D L A 0 D R V E E L A 6 D 1 1 2 2 2 2 2 3 5 9 4 5 5 5 5 5 6 D4 F AVC C RESI SCAN RESE RESE N_ EN RVED RVED VCC VCC VCC VCC VCC RES RESE RES RES RES G R VEE T OUT R VEE R VEE R VEE D D D D _ RESE RESE RESE RESE RESE H RVED RVED RVED RVED RVED RES RES RES RES RES J R VEE R VEE R VEE R VEE R VEE D D D D D RES RES RES RES RES K R VEE R VEE R VEE R VEE R VEE D D D D D L RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE M RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE N RVED RVED RVED RVED RVE VCC D RESE RESE RESE RESE RESE P RVED RVED RVED RVED RVE VCC D RES RES RES RES RESE R R VEE R VEE R VEE R VEE R VE V C C D D D D D RES RES RES RES RESE T R VEE R VEE R VEE R VEE R VE V C C D D D D D RESE RESE T_MO RESE RESE U RVED RVED DE0 RVED RVE D RESE RESE RESE RESE RESE V RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE W RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE Y RVED RVED RVED RVED RVED A RESE RESE RESE RESE RESE A RVED RVED RVED RVED RVED A RESE RESE RESE RESE RESE B RVED RVED RVED RVED RVED A RESE RESE RESE RESE RESE C RVED RVED RVED RVED RVED A RESE RESE RESE RESE RESE D RVED RVED RVED RVED RVED VCC VCC VCC VCC VCC VDD VDD VDD VDD VCC RESE RESE RESE RESE RVED RVED RVED RVED RESE VCC RVE RESE RESE RESE RESE RVED RVED RVED RVED D RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE M23_ M23_ M23_ RVED RVED CRS RXD0 RXD1 RESE RESE M23_ M23_ M23_ RVED RVED TXD1 TXD0 TXEN A M0_T M0_T M0_T M3_T M3_T M3_R M5_T M5_T M5_R M8_T M8_T M8_R M10_ M10_ M10_ M13_ M16_ M15_ M16_ M15_ M15_ M18_ M18_ M18_ M20_ M20_ M20_ M22_ E XEN XD0 XD1 XD1 XEN XD0 XD1 XEN XD0 XD1 XEN XD0 TXD1 TXEN RXD0 TXD1 TXD0 TXD1 RXD1 TXEN RXD0 TXD1 TXEN RXD0 TXD1 TXEN RXD0 RXD1 R R 0_ T 3_ R T 5_ R T 8_ R M10 M10 M13 M13 R M15 M17 M18 M20 M20 M22 A F M 0 _1 M 0 _0 MR S C M 3 _0 MR S C M 3 _1 M 5 _0 MR S C M 5 _1 M 8 _0 MR S C M 8 _1 T X D _ M 1 0 _ R X D _ T X D _ M 1 3 _ R X D _ M 1 4 _ M 1 60 R X D _ R X D _ M 1 7 _ R X D _ T X D _ M 2 0 _ R X D _ R X D _ M 2 2 _ XD XD XD XD XD XD XD XD 0 CRS 1 0 CRS 1 CRS XD 1 0 CRS 1 0 CRS 1 0 CRS A M1_T M1_T M1_T M2_T M2_C M4_T M4_C M6_T M6_C M7_T M7_C M9_T M9_C M11_ M11_ M12_ M12_ M14_ M15_ M16_ M16_ M18_ M18_ M19_ M19_ M21_ M21_ M22_ M22_ RS XD1 RS XD1 RS XD1 RS XD1 RS TXD1 CRS TXD1 CRS TXD1 TXD0 TXD1 CRS TXD0 CRS TXD1 CRS TXD1 CRS TXEN TXD0 G XEN XD0 XD1 XD1 A H AJ 1 2 M1_R M1_C M2_T M2_R M4_T M4_R M6_T M6_R M7_T M7_R M9_T M9_R M11_ M11_ M12_ M12_ M14_ M14_ M13_ M15_ M17_ M17_ M19_ M19_ M21_ M21_ M22_ XD0 RS XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 TXD0 RXD0 TXD0 RXD0 TXD0 RXD0 RXD0 CRS TXD0 RXD1 TXD0 RXD0 TXD0 RXD0 TXD1 M1_R M2_T M2_R M4_T M4_R M6_T M6_R M7_T M7_R M9_T M9_R M11_ M11_ M12_ M12_ M14_ M14_ M16_ M13_ M17_ M17_ M19_ M19_ M21_ M21_ XD1 XEN XD1 XEN XD1 XEN XD1 XEN XD1 XEN XD1 TXEN RXD1 TXEN RXD1 TXEN RXD1 TXEN TXEN TXEN TXD1 TXEN RXD1 TXEN RXD1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 67 Zarlink Semiconductor Inc. MVTX2601 13.2 Ball - Signal Descriptions Data Sheet All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive. 13.2.1 Ball Signal Descriptions Ball No(s) Symbol I/O Description I2C Interface Note: Use I2C and Serial control interface to configure the system A24 A25 Serial Control Interface A26 B26 C25 Frame Buffer Interface SCL SDA Output I/O-TS with pull up I2C Data Clock I2C Data I/O STROBE D0 AUTOFD Input with weak internal pull up Input Output with pull up Serial Strobe Pin Serial Data Input Serial Data Output (AutoFD) D20, B21, D19, E19,D18, E18, D17, E17, D16, E16, D15, E15, D14, E14, D13, E13, D21, E21, A18, B18, C18, A17, B17, C17, A16, B16, C16, A15, B15, C15, A14, B14, D9, E9, D8, E8, D7, E7, D6, E6, D5, E5, D4, E4, D3, E3, D2, E2, A7, B7, A6, B6, C6, A5, B5, C5, A4, B4, C4, A3, B3, C3, B2, C2 C14, A13, B13, C13, A12, B12, C12, A11, B11, C11, D11, E11, A10, B10, D10, E10, A8, C7 B8 C1 C9 D12 LA_D[63:0] I/O-TS with pull up Frame Bank A- Data Bit [63:0] LA_A[20:3] Output Frame Bank A - Address Bit [20:3] LA_ADSC# LA_CLK LA_WE# LA_WE0# Output with pull up Output Output with pull up Output with pull up Frame Bank A Address Status Control Frame Bank A Clock Input Frame Bank A Write Chip Select for one layer SRAM application Frame Bank A Write Chip Select for lower layer of two layers SRAM application Frame Bank A Write Chip Select for upper layer of two layers SRAM application E12 LA_WE1# Output with pull up 68 Zarlink Semiconductor Inc. MVTX2601 Ball No(s) C8 Symbol LA_OE# I/O Output with pull up Data Sheet Description Frame Bank A Read Chip Select for one layer SRAM application Frame Bank A Read Chip Select for lower layer of two layers SRAM application Frame Bank A Read Chip Select for upper layer of two layers SRAM application A9 LA_OE0# Output with pull up B9 LA_OE1# Output with pull up Fast Ethernet Access Ports [23:0] RMII R28 M_MDC Output MII Management Data Clock - (Common for all MII Ports [23:0]) MII Management Data I/O - (Common for all MII Ports - [23:0])) Reference Input Clock Ports [23:0] - Receive Data Bit [1] P28 M_MDIO I/O-TS with pull up R29 AC29, AE28, AJ27, AF27, AJ25, AF24, AH23, AE19, AF21, AJ19, AF18, AJ17, AJ15, AF15, AJ13, AF12, AJ11, AJ9, AF9, AJ7, AF6, AJ5, AJ3, AF1 AC28, AF28, AH27, AE27, AH25, AE24, AF22, AF20, AE21, AH19, AH20, AH17, AH15, AE15, AH13, AE12, AH11, AH9, AE9, AH7, AE6, AH5, AH2, AF2 AC27, AF29, AG27, AF26, AG25, AG23, AF23, AG21, AH21, AF19, AF17, AG17, AG15, AF14, AG13, AF11, AG11, AG9, AF8, AG7, AF5, AG5, AH3, AF3 AD29, AG28, AJ26, AE26, AJ24, AE23, AJ22, AJ20, AE20, AJ18, AJ21, AJ16, AJ14, AE14, AJ12, AE11, AJ10, AJ8, AE8, AJ6, AE5, AJ4, AG1, AE1 M_CLKI M[23:0]_RXD[1] Input Input with weak internal pull up resistors. M[23:0]_RXD[0] Input with weak internal pull up resistors Ports [23:0] - Receive Data Bit [0] M[23:0]_CRS_DV Input with weak internal pull down resistors. Ports [23:0] - Carrier Sense and Receive Data Valid M[23:0]_TXEN I/O- TS with pull up, slew Ports [23:0] - Transmit Enable Strap option for RMII/GPSI 69 Zarlink Semiconductor Inc. MVTX2601 Ball No(s) AD27, AH28, AG26, AE25, AG24, AE22, AJ23, AG20, AE18, AG18, AE16, AG16, AG14, AE13, AG12, AE10, AG10, AG8, AE7, AG6, AE4, AG4, AG3, AE3 AD28, AG29, AH26, AF25, AH24, AG22, AH22, AE17, AG19, AH18, AF16, AH16, AH14, AF13, AH12, AF10, AH10, AH8, AF7, AH6, AF4, AH4, AG2, AE2 LED Interface C29 D29 E29 B27, A27, E28, D28, C28, B28 C27 D27 C26 D26 D25 D24 E24 Trunk Enable C22 TRUNK0 Input w/ weak internal pull down resistors Trunk Port Enable LED_CLK/TSTOUT0 LED_SYN/TSTOUT1 LED_BIT/TSTOUT2 TSTOUT[8:3] INIT_DONE/TSTOUT 9 INIT_START/TSTOU T10 CHECKSUM_OK/TS TOUT11 FCB_ERR/TSTOUT1 2 MCT_ERR/TSTOUT1 3 BIST_IN_PRC/TSTO UT14 BIST_DONE/TSTOU T15 I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up Symbol M[23:0]_TXD[1] I/O Output, slew Data Sheet Description Ports [23:0] - Transmit Data Bit [1] M[23:0]_TXD[0] Output, slew Ports [23:0] - Transmit Data Bit [0] LED Serial Interface Output Clock LED Output Data Stream Envelope LED Serial Data Output Stream (Reserved) System start operation Start initialization EEPROM read OK FCB memory self test fail MCT memory self test fail Processing memory self test Memory self test done 70 Zarlink Semiconductor Inc. MVTX2601 Ball No(s) A21 Test Facility U3 T_MODE0 I/O-TS Symbol TRUNK1 I/O Input w/ weak internal pull down resistors Data Sheet Description Trunk Port Enable Test Pin - Set Mode upon Reset, and provides NAND Tree test output during test mode (Pull Up) Test Pin - Set Mode upon Reset, and provides NAND Tree test output during test mode (Pull Up) T_MODE1 T_MODE0 0 0 NandTree 0 1 Reserved 1 0 reserved 1 1 Regular operation T_MODE0 and T_MODE1 are used for manufacturing tests. The signals should both be set to 1 for regular operation. Scan Enable 0 - Normal mode (unconnected) 1 - Enables Test mode 0 - Normal mode (unconnected) C10 T_MODE1 I/O-TS F3 E27 SCAN_EN SCANMODE Input with pull down Input with pull down System Clock, Power and Ground Pins E1 K12, K13, K17,K18 M10, N10, M20, N20, U10, V10, U20, V20, Y12, Y13, Y17, Y18 F13, F14, F15, F16, F17, N6, P6, R6, T6, U6, N24, P24, R24, T24, U24, AD13, AD14, AD15, AD16, AD17 SCLK VDD Input Power System Clock at 100 MHz +2.5 Volt DC Supply VCC Power +3.3 Volt DC Supply 71 Zarlink Semiconductor Inc. MVTX2601 Ball No(s) M12, M13, M14, M15, M16, M17, M18, N12, N13, N14, N15, N16, N17, N18, P12, P13, P14, P15, P16, P17, P18, R12, R13, R14, R15, R16, R17, R18, T12, T13, T14, T15, T16, T17, T18, U12, U13, U14, U15, U16, U17, U18, V12, V13, V14, V15, V16, V17, V18, F1 D1 MISC D22 D23 E23 F2 G2 SCANCOL SCANCLK SCANLINK RESIN# RESETOUT# Input Input/ output Input Input Output VSS Symbol I/O Power Ground Ground Data Sheet Description AVCC AGND Analog Power Analog Ground Analog +2.5 Volt DC Supply Analog Ground Scans the Collision signal of Home PHY Clock for scanning Home PHY collision and link Link up signal from Home PHY Reset Input Reset PHY 72 Zarlink Semiconductor Inc. MVTX2601 Ball No(s) B22, F4, F5, G4, G5, H4, H5, J4, J5, K4, K5, L4, L5, M4, M5, N4, N5, G3, H1, H2, H3, J1, J2, J3, K1, K2, K3, L1, L2, L3, M1, M2, M3, U4, U5, V4, V5, W4, W5, Y4, Y5, AA4, AA5, AB4, AB5, AC4, AC5, AD4, AD5, W1, Y1, Y2, Y3, AA1, AA2, AA3, AB1, AB2, AB3, AC1, AC2, AC3, AD1, AD2, AD3, N3, N2, N1, P3, P2, P1, R5, R4, R3, R2, R1, T5, T4, T3, T2, T1, W3, W2, V1, G1, V3, P4, P5, V2, U1, U2, U26, U25, V26, V25, W26, W25, Y27, Y26, AA26, AA25, AB26, AB25, AC26, AC25, AD26, AD25, T28, U28, R25, U29, T29, U27, V29, V28, V27, W29, W28, W27, Y29, Y28, Y25, AA29, AA28, AA27, AB29, AB28, AB27, T26, R26, T27, T25, P29, G26, G25, H26, H25, J26, J25, K25, K26, M25, L26, M26, L25, N26, N25, P26, P25, F28, G28, E25, G29, F29, G27,H29, H28, H27, J29, J28, J27, K29, K28, K27, L29, L28, L27, M29, M28, M27, F26, E26, F27, F25, N29,B24, E20, B25 Symbol Reserved I/O-TS I/O Data Sheet Description Reserved Pins. Leave unconnected. Bootstrap Pins (Default= pull up, 1= pull up 0= pull down) After reset TSTOUT0 to TSTOUT15 are used by the LED interface. C29 D29 TSTOUT0 TSTOUT1 Default: Enable (1) Reserved RMII MAC Power Saving Enable 0 - No power saving 1 - Power saving Reserved Default: SCLK (1) Scan Speed 0 - 1/4 SCLK(HPNA) 1 - SCLK C28, B28, E29 D28 TSTOUT[4:2] TSTOUT5 73 Zarlink Semiconductor Inc. MVTX2601 Ball No(s) E28 A27 Symbol TSTOUT6 TSTOUT7 Default: 128 K x 32 or 128 K x 64 (1) I/O Reserved Data Sheet Description Memory Size 0 - 256 K x 32 or 256 K x 64 (4 M total) 1 - 128 K x 32 or 128 K x 64 (2 M total) EEPROM Installed 0 - EEPROM installed 1 - EEPROM not installed MCT Aging 0 - MCT aging disable 1 - MCT aging enable FCB Aging 0 - FCB aging disable 1 - FCB aging enable Timeout Reset 0 - Time out reset disable 1 - Time out reset enable. Issue reset if any state machine did not go back to idle for 5 Sec. Reserved B27 TSTOUT8 Default: Not Installed (1) Default: MCT aging enable (1) Default: FCB aging enable (1) Default: Timeout reset enable (1) C27 TSTOUT9 D27 TSTOUT10 C26 TSTOUT11 D26 D25 TSTOUT12 TSTOUT13 Default: Single depth (1) FDB RAM depth (1 or 2 layers) 0 - Two layers 1 - One layer Reserved D24 E24 TSTOUT14 TSTOUT15 Default: Normal operation Default: RMII SRAM Test Mode 0 - Enable test mode 1 - Normal operation 0 - GPSI 1 - RMII AD29, AG28, AJ26, AE26, AJ24, AE23, AJ22, AJ20, AE20, AJ18, AJ21, AJ16, AJ14, AE14, AJ12, AE11, AJ10, AJ8, AE8, AJ6, AE5, AJ4, AG1, AE1, C21 C19, B19, A19 M[23:0]_TXEN P_D OE_CLK[2:0] Must be pulled-down Default: 111 Reserved - Must be pulleddown. Programmable delay for internal OE_CLK from SCLK input. The OE_CLK is used for generating the OE0 and OE1 signals Suggested value is 001. 74 Zarlink Semiconductor Inc. MVTX2601 Ball No(s) C20, B20, A20 Symbol LA_CLK[2:0] I/O Default: 111 Data Sheet Description Programmable delay for LA_CLK from internal OE_CLK. The LA_CLK delay from SCLK is the sum of the delay programmed in here and the delay in P_D[15:13]. Suggested value is 011. Dedicated Port Mirror Mode. The first 5 bits select the port to be mirrored. The last bit selects either ingress or egress data. B22, A22, C23, B23, A23, C24 MIRROR[5:0] Default: 111111 # = Active low signal Note: Input = Input signal In-ST = Input signal with Schmitt-Trigger Output = Output signal (Tri-State driver) Out-OD = Output signal with Open-Drain driver I/O-TS = Input & Output signal with Tri-State driver I/O-OD = Input & Output signal with Open-Drain driver 75 Zarlink Semiconductor Inc. MVTX2601 13.3 Ball - Signal Name Signal Name LA_D[63] LA_D[62] LA_D[61] LA_D[60] LA_D[59] LA_D[58] LA_D[57] LA_D[56] LA_D[55] LA_D[54] LA_D[53] LA_D[52] LA_D[51] LA_D[50] LA_D[49] LA_D[48] LA_D[47] LA_D[46] LA_D[45] LA_D[44] LA_D[43] LA_D[42] LA_D[41] LA_D[40] LA_D[39] LA_D[38] LA_D[37] LA_D[36] LA_D[35] LA_D[34] LA_D[33] LA_D[32] LA_D[31] Ball No. D3 E3 D2 E2 A7 B7 A6 B6 C6 A5 B5 C5 A4 B4 C4 A3 B3 C3 B2 C2 C14 A13 B13 C13 A12 B12 C12 A11 B11 C11 D11 E11 A10 Signal Name LA_D[19] LA_D[18] LA_D[17] LA_D[16] LA_D[15] LA_D[14] LA_D[13] LA_D[12] LA_D[11] LA_D[10] LA_D[9] LA_D[8] LA_D[7] LA_D[6] LA_D[5] LA_D[4] LA_D[3] LA_D[2] LA_D[1] LA_D[0] LA_A[20] LA_A[19] LA_A[18] LA_A[17] LA_A[16] LA_A[15] LA_A[14] LA_A[13] LA_A[12] LA_A[11] LA_A[10] LA_A[9] LA_A[8] Ball No. A9 B9 F4 F5 G4 G5 H4 H5 J4 J5 K4 K5 L4 L5 M4 M5 N4 N5 G3 H1 H2 H3 J1 J2 J3 K1 K2 K3 L1 L2 L3 M1 M2 Data Sheet Ball No. D20 B21 D19 E19 D18 E18 D17 E17 D16 E16 D15 E15 D14 E14 D13 E13 D21 E21 A18 B18 C18 A17 B17 C17 A16 B16 C16 A15 B15 C15 A14 B14 D9 Signal Name LA_OE0# LA_OE1# RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 76 Zarlink Semiconductor Inc. MVTX2601 Ball No. E9 D8 E8 D7 E7 D6 E6 D5 E5 D4 E4 AB4 AB5 AC4 AC5 AD4 AD5 W1 Y1 Y2 Y3 AA1 AA2 AA3 AB1 AB2 AB3 AC1 AC2 AC3 AD1 AD2 AD3 N3 N2 Signal Name LA_D[30] LA_D[29] LA_D[28] LA_D[27] LA_D[26] LA_D[25] LA_D[24] LA_D[23] LA_D[22] LA_D[21] LA_D[20] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Ball No. B10 D10 E10 A8 C7 B8 C1 C9 D12 E12 C8 U2 R28 P28 R29 AC29 AE28 AJ27 AF27 AJ25 AF24 AH23 AE19 AF21 AJ19 AF18 AJ17 AJ15 AF15 AJ13 AF12 AJ11 AJ9 AF9 AJ7 Signal Name LA_A[7] LA_A[6] LA_A[5] LA_A[4] LA_A[3] LA_DSC# LA_CLK LA_WE# LA_WE0# LA_WE1# LA_OE# RESERVED MDC MDIO M_CLK M[23]_RXD[1] M[22]_RXD[1] M[21]_RXD[1] M[20]_RXD[1] M[19]_RXD[1] M[18]_RXD[1] M[17]_RXD[1] M[16]_RXD[1] M[15]_RXD[1] M[14]_RXD[1] M[13]_RXD[1] M[12]_RXD[1] M[11]_RXD[1] M[10]_RXD[1] M[9]_RXD[1] M[8]_RXD[1] M[7]_RXD[1] M[6]_RXD[1] M[5]_RXD[1] M[4]_RXD[1] Ball No. M3 U4 U5 V4 V5 W4 W5 Y4 Y5 AA4 AA5 AH7 AE6 AH5 AH2 AF2 AC27 AF29 AG27 AF26 AG25 AG23 AF23 AG21 AH21 AF19 AF17 AG17 AG15 AF14 AG13 AF11 AG11 AG9 AF8 Data Sheet Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M[4]_RXD[0] M[3]_RXD[0] M[2]_RXD[0] M[1]_RXD[0] M[0]_RXD[0] M[23]_CRS_DV M[22]_CRS_DV M[21]_CRS_DV M[20]_CRS_DV M[19]_CRS_DV M[18]_CRS_DV M[17]_CRS_DV M[16]_CRS_DV M[15]_CRS_DV M[14]_CRS_DV M[13]_CRS_DV M[12]_CRS_DV M[11]_CRS_DV M[10]_CRS_DV M[9]_CRS_DV M[8]_CRS_DV M[7]_CRS_DV M[6]_CRS_DV M[5]_CRS_DV 77 Zarlink Semiconductor Inc. MVTX2601 Ball No. N1 P3 P2 P1 R5 R4 R3 R2 R1 T5 T4 T3 T2 T1 W3 W2 V1 G1 V3 P4 P5 V2 U1 AE8 AJ6 AE5 AJ4 AG1 AE1 AD27 AH28 AG26 AE25 AG24 AE22 Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M[5]_TXEN M[4]_TXEN M[3]_TXEN M[2]_TXEN M[1]_TXEN M[0]_TXEN M[23]_TXD[1] M[22]_TXD[1] M[21]_TXD[1] M[20]_TXD[1] M[19]_TXD[1] M[18]_TXD[1] Ball No. AF6 AJ5 AJ3 AF1 AC28 AF28 AH27 AE27 AH25 AE24 AF22 AF20 AE21 AH19 AH20 AH17 AH15 AE15 AH13 AE12 AH11 AH9 AE9 AH8 AF7 AH6 AF4 AH4 AG2 AE2 U26 U25 V26 V25 W26 Signal Name M[3]_RXD[1] M[2]_RXD[1] M[1]_RXD[1] M[0]_RXD[1] M[23]_RXD[0] M[22]_RXD[0] M[21]_RXD[0] M[20]_RXD[0] M[19]_RXD[0] M[18]_RXD[0] M[17]_RXD[0] M[16]_RXD[0] M[15]_RXD[0] M[14]_RXD[0] M[13]_RXD[0] M[12]_RXD[0] M[11]_RXD[0] M[10]_RXD[0] M[9]_RXD[0] M[8]_RXD[0] M[7]_RXD[0] M[6]_RXD[0] M[5]_RXD[0] M[6]_TXD[0] M[5]_TXD[0] M[4]_TXD[0] M[3]_TXD[0] M[2]_TXD[0] M[1]_TXD[0] M[0]_TXD[0] RESERVED RESERVED RESERVED RESERVED RESERVED Ball No. AG7 AF5 AG5 AH3 AF3 AD29 AG28 AJ26 AE26 AJ24 AE23 AJ22 AJ20 AE20 AJ18 AJ21 AJ16 AJ14 AE14 AJ12 AE11 AJ10 AJ8 G27 H29 H28 H27 J29 J28 J27 K29 K28 K27 L29 L28 Data Sheet Signal Name M[4]_CRS_DV M[3]_CRS_DV M[2]_CRS_DV M[1]_CRS_DV M[0]_CRS_DV M[23]_TXEN M[22]_TXEN M[21]_TXEN M[20]_TXEN M[19]_TXEN M[18]_TXEN M[17]_TXEN M[16]_TXEN M[15]_TXEN M[14]_TXEN M[13]_TXEN M[12]_TXEN M[11]_TXEN M[10]_TXEN M[9]_TXEN M[8]_TXEN M[7]_TXEN M[6]_TXEN RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 78 Zarlink Semiconductor Inc. MVTX2601 Ball No. AJ23 AG20 AE18 AG18 AE16 AG16 AG14 AE13 AG12 AE10 AG10 AG8 AE7 AG6 AE4 AG4 AG3 AE3 AD28 AG29 AH26 AF25 AH24 AG22 AH22 AE17 AG19 AH18 AF16 AH16 AH14 AF13 AH12 AF10 Signal Name M[17]_TXD[1] M[16]_TXD[1] M[15]_TXD[1] M[14]_TXD[1] M[13]_TXD[1] M[12]_TXD[1] M[11]_TXD[1] M[10]_TXD[1] M[9]_TXD[1] M[8]_TXD[1] M[7]_TXD[1] M[6]_TXD[1] M[5]_TXD[1] M[4]_TXD[1] M[3]_TXD[1] M[2]_TXD[1] M[1]_TXD[1] M[0]_TXD[1] M[23]_TXD[0] M[22]_TXD[0] M[21]_TXD[0] M[20]_TXD[0] M[19]_TXD[0] M[18]_TXD[0] M[17]_TXD[0] M[16]_TXD[0] M[15]_TXD[0] M[14]_TXD[0] M[13]_TXD[0] M[12]_TXD[0] M[11]_TXD[0] M[10]_TXD[0] M[9]_TXD[0] M[8]_TXD[0] Ball No. W25 Y27 Y26 AA26 AA25 AB26 AB25 AC26 AC25 AD26 AD25 U27 V29 V28 V27 W29 W28 W27 Y29 Y28 Y25 AA29 AA28 AA27 AB29 AB28 AB27 R26 T25 T26 T28 U28 R25 U29 Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Ball No. L27 M29 M28 M27 G26 G25 H26 H25 J26 J25 K25 K26 M25 L26 M26 L25 N26 N25 P26 P25 F28 G28 E25 G29 F29 F26 E26 F25 E24 D24 D25 D26 C26 D27 Data Sheet Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BIST_DONE/TSTOUT[15] BIST_IN_PRC/TST0UT[14] MCT_ERR/TSTOUT[13] FCB_ERR/TSTOUT[12] CHECKSUM_OK/TSTOUT[1 1] INIT_START/TSTOUT[10] 79 Zarlink Semiconductor Inc. MVTX2601 Ball No. AH10 B27 A27 E28 D28 C28 B28 E29 D29 C29 N29 P29 F3 E1 U3 C10 B24 A21 C22 A26 B26 C25 A24 A25 F1 D1 D22 E23 E27 N28 N27 F2 G2 RESIN# RESETOUT# Signal Name M[7]_TXD[0] TSTOUT[8] TSTOUT[7] TSTOUT[6] TSTOUT[5] TSTOUT[4] TSTOUT[3] LED_BIT/TSTOUT[2] LED_SYN/TSTOUT[1 ] LED_CLK/TSTOUT[0 ] RESERVED RESERVED SCAN_EN SCLK T_MODE0 T_MODE1 RESERVED TRUNK1 TRUNK0 STROBE D0 AUTOFD SCL SDA AVCC AGND SCANCOL SCANLINK SCANMODE Ball No. T29 U18 V12 V13 V14 V15 V16 V17 V18 N14 N15 N16 N17 N18 P12 P13 P14 P15 P16 C19 B19 A19 R13 R14 R15 R16 R17 R18 T12 T13 T14 T15 T16 Signal Name RESERVED VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS OE_CLK2 OE_CLK1 OE_CLK0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball No. C27 N12 N13 K17 K18 M10 N10 M20 N20 U10 V10 U20 V20 Y12 Y13 Y17 Y18 K12 K13 M16 M17 M18 F16 F17 N6 P6 R6 T6 U6 N24 P24 R24 T24 Data Sheet Signal Name INIT_DONE/TSTOUT[9] VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 80 Zarlink Semiconductor Inc. MVTX2601 Ball No. B22 A22 C23 B23 A23 C24 D23 T27 F27 C20 B20 A20 C21 E20 B25 Signal Name MIRROR5 MIRROR4 MIRROR3 MIRROR2 MIRROR1 MIRROR0 SCANCLK RESERVED RESERVED LA_CLK2 LA_CLK1 LA_CLK0 P_D RESERVED RESERVED Ball No. T17 T18 U12 U13 U14 U15 U16 U17 M12 M13 M14 M15 P17 P18 R12 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball No. U24 AD13 AD14 AD15 AD16 AD17 F13 F14 F15 Data Sheet Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC 13.4 13.4.1 AC/DC Timing Absolute Maximum Ratings -65C to +150C -40C to +85C +125C +3.0 V to +3.6 V +2.38 V to +2.75 V -0.5 V to (VCC + 3.3 V) Storage Temperature Operating Temperature Maximum Junction Temperature Supply Voltage VCC with Respect to VSS Supply Voltage VDD with Respect to VSS Voltage on Input Pins Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied. 13.4.2 DC Electrical Characteristics VCC = 3.0 V to 3.6 V (3.3v +/- 10%)TAMBIENT = -40C to +85C VDD = 2.5V +10% - 5% 81 Zarlink Semiconductor Inc. MVTX2601 13.4.3 Recommended Operating Conditions Parameter Description Frequency of Operation Supply Current - @ 100 MHz (VCC=3.3 V) Supply Current - @ 100 MHz (VDD=2.5 V) Output High Voltage (CMOS) Output Low Voltage (CMOS) Input High Voltage (TTL 5 V tolerant) Input Low Voltage (TTL 5 V tolerant) Input Leakage Current (0.1 V < VIN < VCC)(all pins except those with internal pull-up/pull-down resistors) Output Leakage Current (0.1 V < VOUT < VCC) Input Capacitance Output Capacitance I/O Capacitance Thermal resistance with 0 air flow Thermal resistance with 1 m/s air flow Thermal resistance with 2 m/s air flow Thermal resistance between junction and case Thermal resistance between junction and board 2.0 2.4 0.4 Min. Typ. 100 450 1500 Max. Data Sheet Symbol fosc ICC IDD VOH VOL VIH-TTL VIL-TTL IIL Unit MHz mA mA V V V V A VCC + 2.0 0.8 10 IOL CIN COUT CI/O ja ja ja jc jb 10 5 5 7 11.2 10.2 8.9 3.1 6.6 A pF pF pF C/W C/W C/W C/W C/W 13.4.4 Typical Reset & Bootstrap Timing Diagram RESIN# RESETOUT# Tri-Stated R1 R3 Bootstrap Pins Outputs Inputs R2 Outputs Figure 13 - Typical Reset & Bootstrap Timing Diagram 82 Zarlink Semiconductor Inc. MVTX2601 Symbol R1 R2 R3 Parameter Delay until RESETOUT# is tri-stated Bootstrap stabilization RESETOUT# assertion 1 s Min. Typ. 10ns 10 s 2 ms Table 10 - Reset & Bootstrap Timing a. The TSTOUT[8:0] pins will switch over to the LED interface functionality in 3 SCLK cycles after RESIN# goes high Data Sheet Note RESETOUT# state is then determined by the external pull-up/down resistor Bootstrap pins sampled on rising edge of RESIN#a 13.5 13.5.1 Local Frame Buffer SBRAM Memory Interface Local SBRAM Memory Interface LA_CLK L1 LA_D[63:0] L2 Figure 14 - Local Memory Interface - Input Setup and Hold Timing LA_CLK L3-max L3-min LA_D[63:0] L4-max L4-min LA_A[20:3] L6-max L6-min LA_ADSC#] L3-max L3-min LA_WE[1:0]# #### L3-max L3-min LA_OE[1:0]# L3-max L3-min LA_WE# L3-max L3-min LA_OE# Figure 15 - Local Memory Interface - Output Valid Delay Timing 83 Zarlink Semiconductor Inc. MVTX2601 AC Characteristics - Local frame buffer SBRAM Memory Interface -100 MHz Symbol L1 L2 L3 L4 L6 L7 L8 L9 L10 Parameter Min. (ns) LA_D[63:0] input set-up time LA_D[63:0] input hold time LA_D[63:0] output valid delay LA_A[20:3] output valid delay LA_ADSC# output valid delay LA_WE[1:0]#output valid delay LA_OE[1:0]# output valid delay LA_WE# output valid delay LA_OE# output valid delay 4 1.5 1.5 2 1 1 -1 1 1 7 7 7 7 1 7 5 Max. (ns) Note Data Sheet CL = 25 pf CL = 30 pf CL = 30 pf CL = 25 pf CL = 25 pf CL = 25 pf CL = 25 pf 13.6 13.6.1 AC Characteristics Reduced Media Independent Interface -50 MHz Symbol M2 M3 M4 M5 M6 M7 Parameter Min. (ns) M[23:0]_RXD[1:0] Input Setup Time M[23:0]_RXD[1:0] Input Hold Time M[23:0]_CRS_DV Input Setup Time M[23:0]_CRS_DV Input Hold Time M[23:0]_TXEN Output Delay Time M[23:0]_TXD[1:0] Output Delay Time 4 1 4 1 2 2 11 11 Max. (ns) Note CL = 20 pF CL = 20 pF Table 11 - AC Characteristics - Reduced Media Independent Interface M_CLKI M6-max M6-min M[23:0]_TXEN M7-max M7-min M[23:0]_TXD[1:0] Figure 16 - AC Characteristics - Reduced Media Independent Interface 84 Zarlink Semiconductor Inc. MVTX2601 M_CLKI M2 M[23:0]_RXD M4 M[23:0]_CRS_DV M5 M3 Data Sheet Figure 17 - AC Characteristics - Reduced Media Independent Interface 13.6.2 LED Interface LED_CLK LE5-max LE5-min LED_SYN LE6-max LE6-min LED_BIT Figure 18 - AC Characteristics - LED Interface Variable FREQ. Min. (ns) -1 -1 Max. (ns) 7 7 Symbol LE5 LE6 Parameter LED_SYN Output Valid Delay LED_BIT Output Valid Delay Note CL = 30 pf CL = 30 pf Table 12 - AC Characteristics - LED Interface 13.6.3 SCANLINK SCANCOL Output Delay Timing SCANCLK C5-max C5-min SCANLINK C7-max C7-min SCANCOL Figure 19 - SCANLINK SCANCOL Output Delay Timing 85 Zarlink Semiconductor Inc. MVTX2601 SCANCLK C1 SCANLINK C3 SCANCOL C4 C2 Data Sheet Figure 20 - SCANLINK, SCANCOL Setup Timing -25 MHz Symbol C1 C2 C3 C4 C5 C7 Parameter Min. (ns) SCANLINK input set-up time SCANLINK input hold time SCANCOL input setup time SCANCOL input hold time SCANLINK output valid delay SCANCOL output valid delay 20 2 20 1 0 0 10 10 CL = 30 pf CL = 30 pf Max (ns) Note Table 13 - SCANLINK, SCANCOL Timing 86 Zarlink Semiconductor Inc. MVTX2601 13.6.4 MDIO Input Setup and Hold Timing MDC D1 MDIO Data Sheet D3 Figure 21 - MDIO Input Setup and Hold Timing MDC D3-max D3-min MDIO Figure 22 - MDIO Output Delay Timing 1 MHz Symbol D1 D2 D3 Parameter Min. (ns) MDIO input setup time MDIO input hold time MDIO output delay time 10 2 1 Table 14 - MDIO Timing 20 CL = 50 pf Max. (ns) Note 87 Zarlink Semiconductor Inc. MVTX2601 13.6.5 I2C Input Setup Timing SCL S1 SDA S2 Data Sheet Figure 23 - I 2C Input Setup Timing SCL S3-max S3-min SDA Figure 24 - I2C Output Delay Timing 50 KHz Symbol S1 S2 S3* Parameter Min. (ns) SDA input setup time SDA input hold time SDA output delay time 20 1 4 usec 6 usec CL = 30 pf Max. (ns) Note * Open Drain Output. Low to High transistor is controlled by external pullup resistor. Table 15 - I2C Timing 88 Zarlink Semiconductor Inc. MVTX2601 13.6.6 Serial Interface Setup Timing STROBE D1 D0 D2 D4 D5 D1 D2 Data Sheet Figure 25 - Serial Interface Setup Timing STROBE D3-max D3-min AutoFd Figure 26 - Serial Interface Output Delay Timing Symbol D1 D2 D3 D4 D5 D0 setup time D0 hold time Parameter Min. (ns) 20 3 s 1 5 s 5 s Max. (ns) Note AutoFd output delay time Strobe low time Strobe high time 50 CL = 100 pf Table 16 - Serial Interface Timing 89 Zarlink Semiconductor Inc. E1 E DIMENSION A A1 A2 D D1 E E1 b e MIN MAX 2.20 2.46 0.50 0.70 1.17 REF 37.70 37.30 34.50 REF 37.70 37.30 34.50 REF 0.60 0.90 1.27 553 Conforms to JEDEC MS - 034 e D D1 A2 b NOTE: 1. CONTROLLING DIMENSIONS ARE IN MM 2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. N IS THE NUMBER OF SOLDER BALLS 5. NOT TO SCALE. 6. SUBSTRATE THICKNESS IS 0.56 MM Package Code ISSUE ACN DATE APPRD. Previous package codes: For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. 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